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1. WO2011104777 - SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

Publication Number WO/2011/104777
Publication Date 01.09.2011
International Application No. PCT/JP2010/005202
International Filing Date 24.08.2010
IPC
H01L 21/3205 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/322 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
322to modify their internal properties, e.g. to produce internal imperfections
H01L 23/52 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
H01L 25/065 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 25/07 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
07the devices being of a type provided for in group H01L29/78
H01L 25/18 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
CPC
H01L 21/3221
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
322to modify their internal properties, e.g. to produce internal imperfections
3221of silicon bodies, e.g. for gettering
H01L 21/76898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76898formed through a semiconductor substrate
H01L 2224/73204
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73201on the same surface
73203Bump and layer connectors
73204the bump connector being embedded into the layer connector
H01L 2225/06513
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2225Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/00
06503Stacked arrangements of devices
06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
H01L 2225/06544
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2225Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/00
06503Stacked arrangements of devices
06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
06544Design considerations for via connections, e.g. geometry or layout
H01L 23/26
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
16Fillings or auxiliary members in containers ; or encapsulations; , e.g. centering rings
18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
26including materials for absorbing or reacting with moisture or other undesired substances ; , e.g. getters
Applicants
  • パナソニック株式会社 PANASONIC CORPORATION [JP]/[JP] (AllExceptUS)
  • 西尾太一 NISHIO, Taichi (UsOnly)
Inventors
  • 西尾太一 NISHIO, Taichi
Agents
  • 前田弘 MAEDA, Hiroshi
Priority Data
2010-03713223.02.2010JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract
(EN) A semiconductor substrate (1) has a first surface (1a), which is an element formation surface, and a second surface (1b) on the opposite side. A through-hole (20) is formed so as to penetrate the semiconductor substrate from the first surface (1a) to the second surface (1b). An insulating film (21) and a barrier film (22) are successively formed on the inner wall of the through-hole (20). A conductor (23) is formed so as to fill the through-hole (20) in which the insulating film (21) and the barrier film (22) have been formed. A gettering site (30) is formed on at least the first surface (1a) side of the semiconductor substrate (1) in the area surrounding the through-hole (20).
(FR) L'invention concerne un substrat semi-conducteur (1) qui comporte une première surface (1a) qui est une surface de formation d'éléments, et une deuxième surface (1b) sur le côté opposé. Un trou traversant (20) est formé de manière à pénétrer le substrat semi-conducteur de la première surface (1a) à la deuxième surface (1b). Un film isolant (21) et un film barrière (22) sont successivement formés sur la paroi interne du trou traversant (20). Un conducteur (23) est formé de manière à remplir le trou traversant (20) dans lequel le film isolant (21) et le film barrière (22) ont été formés. Un site de piégeage (30) est formé au moins sur la première surface (1a) du substrat semi-conducteur (1), dans la zone entourant le trou traversant (20).
(JA)  半導体基板(1)は、素子形成面である第1の面(1a)及びその反対側の第2の面(1b)を有する。第1の面(1a)から第2の面(1b)まで半導体基板(1)を貫通するように貫通孔(20)が形成されている。貫通孔(20)の内壁上に絶縁膜(21)及びバリア膜(22)が順次形成されている。絶縁膜(21)及びバリア膜(22)が形成された貫通孔(20)が埋まるように導電部(23)が形成されている。貫通孔(20)の周辺に位置する部分の半導体基板(1)における少なくとも第1の面(1a)側にゲッタリングサイト(30)が形成されている。
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