Processing

Please wait...

Settings

Settings

Goto Application

1. WO2011100100 - MEMORY CELL FORMED USING A RECESS AND METHODS FOR FORMING THE SAME

Publication Number WO/2011/100100
Publication Date 18.08.2011
International Application No. PCT/US2011/022096
International Filing Date 21.01.2011
IPC
H01L 27/28 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
28including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
B82Y 40/00 2011.1
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE  OR TREATMENT OF NANOSTRUCTURES
40Manufacture or treatment of nanostructures
B82Y 10/00 2011.1
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE  OR TREATMENT OF NANOSTRUCTURES
10Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 29/06 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
CPC
B82Y 10/00
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
10Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
B82Y 40/00
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
40Manufacture or treatment of nanostructures
H01L 27/1021
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
102including bipolar components
1021including diodes only
H01L 27/2409
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, ; e.g. resistance switching non-volatile memory structures
2409comprising two-terminal selection components, e.g. diodes
H01L 27/2463
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, ; e.g. resistance switching non-volatile memory structures
2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
H01L 27/2481
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, ; e.g. resistance switching non-volatile memory structures
2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
2481arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
Applicants
  • SANDISK 3D, LLC [US]/[US] (AllExceptUS)
  • MAXWELL, Steven [US]/[US] (UsOnly)
Inventors
  • MAXWELL, Steven
Agents
  • DUGAN, Brian, M.
Priority Data
12/703,90711.02.2010US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY CELL FORMED USING A RECESS AND METHODS FOR FORMING THE SAME
(FR) CELLULE MÉMOIRE FORMÉE EN UTILISANT UN RENFONCEMENT ET SES PROCÉDÉS DE FORMATION
Abstract
(EN) In a first aspect, a method of forming a memory cell is provided, the method including: (1) forming a pillar above a substrate, the pillar comprising a steering element and a metal hardmask layer; (2) selectively removing the metal hardmask layer to create a void; and (3) forming a carbon-based switching material within the void. Numerous other aspects are provided.
(FR) Selon un premier aspect, cette invention concerne un procédé de formation d'une cellule mémoire. Ledit procédé comprend les étapes consistant à : (1) former un pilier sur un substrat, le pilier comprenant un élément de direction et une couche de masque dur métallique ; (2) éliminer sélectivement la couche de masque dur métallique pour créer un espace vide ; et (3) former un matériau de commutation à base de carbone à l'intérieur de l'espace vide. Cette invention couvre de nombreux autres aspects.
Related patent documents
Latest bibliographic data on file with the International Bureau