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1. WO2011072527 - VERTICAL SOI BIPOLAR TRANSISTOR AND MAKING METHOD THEREOF

Publication Number WO/2011/072527
Publication Date 23.06.2011
International Application No. PCT/CN2010/075156
International Filing Date 14.07.2010
IPC
H01L 29/732 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70Bipolar devices
72Transistor-type devices, i.e. able to continuously respond to applied control signals
73Bipolar junction transistors
732Vertical transistors
H01L 21/331 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33the devices comprising three or more electrodes
331Transistors
CPC
H01L 29/66265
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66234Bipolar junction transistors [BJT]
66265Thin film bipolar transistors
H01L 29/7317
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
70Bipolar devices
72Transistor-type devices, i.e. able to continuously respond to applied control signals
73Bipolar junction transistors
7317Bipolar thin film transistors
Applicants
  • 中国科学院上海微系统与信息技术研究所 SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES [CN]/[CN] (AllExceptUS)
  • 陈静 CHEN, Jing [CN]/[CN] (UsOnly)
  • 罗杰馨 LUO, Jiexin [CN]/[CN] (UsOnly)
  • 伍青青 WU, Qingqing [CN]/[CN] (UsOnly)
  • 周建华 ZHOU, Jianhua [CN]/[CN] (UsOnly)
  • 黄晓橹 HUANG, Xiaolu [SG]/[CN] (UsOnly)
  • 王曦 WANG, Xi [CN]/[CN] (UsOnly)
Inventors
  • 陈静 CHEN, Jing
  • 罗杰馨 LUO, Jiexin
  • 伍青青 WU, Qingqing
  • 周建华 ZHOU, Jianhua
  • 黄晓橹 HUANG, Xiaolu
  • 王曦 WANG, Xi
Agents
  • 上海光华专利事务所 J. Z. M. C PATENT AND TRADEMARK LAW OFFICE
Priority Data
200910201332.517.12.2009CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) VERTICAL SOI BIPOLAR TRANSISTOR AND MAKING METHOD THEREOF
(FR) TRANSISTOR BIPOLAIRE VERTICAL SOI ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种SOI纵向双极晶体管及其制作方法
Abstract
(EN)
A vertical SOI bipolar transistor and a making method thereof are provided. The bipolar transistor includes a SOI substrate, wherein the SOI substrate is composed of a bulk region of the SOI substrate, a buried oxide layer of the SOI substrate, and a top silicon layer from bottom to top; an active region is formed in the top silicon layer of the SOI substrate by STI process; a collector region and a base region are formed in the active region by ion implantation; the collector region is adjacent to the buried oxide layer of the SOI substrate, and the base region is adjacent to the surface of the top silicon layer; an emitter and a base are formed on the base region, and the emitter and the base are surrounded by side-wall oxide spacers (10) respectively. The area of the active region can be reduced, and the integration can be improved by the dual-polysilicon technology. Besides, the compatibility between the SOI BJT and the SOI CMOS can be improved by using the side-wall oxide isolation process, and the SOI Bi-CMOS manufacturing process becomes simple.
(FR)
L'invention concerne un transistor bipolaire vertical SOI et son procédé de fabrication. Ce transistor bipolaire vertical comprend un substrat SOI formé de bas en haut d'une région substrat SOI, d'une couche enterrée d'oxyde SOI et d'une tranche supérieure de silicium, lequel substrat SOI présente une région active formée par STI dans la tranche supérieure de silicium et dans laquelle sont formées par implantation ionique une région électrique adjacente à la couche enterrée d'oxyde SOI et une région de base adjacente à la surface de la tranche supérieure de silicium. Sur la région de base sont formés un émetteur et une électrode de base, lesquels sont respectivement entourés par un espaceur latéral (10) d'oxyde. Grâce à l'utilisation de la technique du transistor bipolaire, on peut réduire la superficie de la région active tout en augmentant le degré d'intégration. Par ailleurs, la technologie d'isolement d'oxyde par espaceur latéral permet d'augmenter la compatibilité entre un SOI BJT et un SOI CMOS avec pour effet de simplifier la technologie utilisant un SOI Bi-CMOS.
(ZH)
提供了一种SOI纵向双极晶体管及其制作方法。该双极晶体管包括SOI衬底,该SOI衬底由下至上为SOI衬底体区、SOI衬底隐埋氧化层以及顶层硅膜,该SOI衬底上采用STI工艺在顶层硅膜中形成有源区,有源区中通过离子注入形成集电区和基区,集电区靠近SOI衬底隐埋氧化层,基区靠近顶层硅膜表面,基区上形成有发射极和基极,发射极和基极分别被侧氧隔离墙(10)包围。通过使用该双多晶硅技术减小了该有源区的面积,并提高了集成度。此外,通过使用侧氧隔离工艺,提高了SOIBJT与SOICMOS的兼容性,使SOIBi-CMOS工艺变得简单。
Also published as
Latest bibliographic data on file with the International Bureau