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1. WO2011038106 - INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY

Publication Number WO/2011/038106
Publication Date 31.03.2011
International Application No. PCT/US2010/049978
International Filing Date 23.09.2010
IPC
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
CPC
G06F 12/0811
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0811with multilevel cache hierarchies
G06F 12/0862
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0862with prefetch
G06F 12/0871
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0866for peripheral storage systems, e.g. disk cache
0871Allocation or management of cache space
G06F 12/0875
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0875with dedicated cache, e.g. instruction or stack
G06F 12/0897
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
0897with two or more cache hierarchy levels
G06F 12/121
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
12Replacement control
121using replacement algorithms
Applicants
  • NVIDIA CORPORATION [US]/[US] (AllExceptUS)
  • NICKOLLS, John, R. [US]/[US] (UsOnly)
  • COON, Brett, W. [US]/[US] (UsOnly)
  • SHEBANOW, Michael, C. [US]/[US] (UsOnly)
Inventors
  • NICKOLLS, John, R.
  • COON, Brett, W.
  • SHEBANOW, Michael, C.
Agents
  • CAREY, John, C.
Priority Data
12/888,40922.09.2010US
61/245,22223.09.2009US
61/246,04025.09.2009US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY
(FR) INSTRUCTIONS POUR GÉRER UNE HIÉRARCHIE DE MÉMOIRES CACHES PARALLÈLES
Abstract
(EN)
A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.
(FR)
L'invention concerne un procédé pour gérer une hiérarchie de mémoires caches parallèles dans une unité de traitement. Le procédé consiste à recevoir une instruction d'une unité de programmateur, l'instruction comportant une instruction de charge ou une instruction de stockage; à déterminer si l'instruction contient un modificateur d'opérations de mise en mémoire cache qui identifie une règle pour la mise en mémoire cache de données associées à l'instruction à un ou plusieurs niveaux de la hiérarchie de mémoires caches parallèles; puis à exécuter l'instruction et à mettre en mémoire cache les données associées à l'instruction en fonction du modificateur d'opérations de mise en mémoire cache.
Also published as
GB1204964.9
Latest bibliographic data on file with the International Bureau