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1. WO2011024481 - DIRECT SAMPLING CIRCUIT AND RECEIVER

Publication Number WO/2011/024481
Publication Date 03.03.2011
International Application No. PCT/JP2010/005325
International Filing Date 30.08.2010
IPC
H03H 19/00 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
19Networks using time-varying elements, e.g. N-path filters
H04B 1/26 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
BTRANSMISSION
1Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
06Receivers
16Circuits
26for superheterodyne receivers
H04B 1/30 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
BTRANSMISSION
1Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
06Receivers
16Circuits
30for homodyne or synchrodyne receivers
CPC
H03H 15/023
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
15Transversal filters
02using analogue shift registers
023with parallel-input configuration
H04B 1/0007
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
BTRANSMISSION
1Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
0003Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
0007wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
Applicants
  • パナソニック株式会社 PANASONIC CORPORATION [JP]/[JP] (AllExceptUS)
  • 森下陽平 MORISHITA, Yohei (UsOnly)
  • 齊藤典昭 SAITO, Noriaki (UsOnly)
Inventors
  • 森下陽平 MORISHITA, Yohei
  • 齊藤典昭 SAITO, Noriaki
Agents
  • 鷲田 公一 WASHIDA, Kimihito
Priority Data
2009-20081631.08.2009JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) DIRECT SAMPLING CIRCUIT AND RECEIVER
(FR) CIRCUIT D'ÉCHANTILLONNAGE DIRECT ET RÉCEPTEUR
(JA) ダイレクトサンプリング回路及び受信機
Abstract
(EN)
Disclosed are a direct sampling circuit and a receiver wherein an excellent frequency characteristic is achieved by use of a relatively simple structure and simple clocks. In each of a plurality of discrete-time circuits (102-1 to 102-4), a charging switch (1021) is on/off controlled by use of one of four-phase control signals. A rotate capacitor (1022) shares, via the charging switch (1021), a charge stored in an IQ generating circuit (101). A dump switch (1023) is on/off controlled by use of another one of the four-phase control signals the phase of which is different from that of the control signal used to on/off control the charging switch (1021). A buffer capacitor (1026) shares, via the dump switch (1023), a charge with the rotate capacitor (1022), thereby forming an output value.
(FR)
La présente invention se rapporte à un circuit d'échantillonnage direct et à un récepteur, une excellente caractéristique de fréquence étant obtenue à l'aide d'une structure relativement simple et de simples horloges. Dans chaque circuit temporel discret d'une pluralité de circuits temporels discrets (102-1 à 102-4), la mise en marche/l'arrêt d'un commutateur de charge (1021) sont commandés à l'aide d'un signal de commande parmi les signaux de commande des quatre phases. Un condensateur rotatif (1022) partage, par l'intermédiaire du commutateur de charge (1021), une charge stockée dans un circuit de génération IQ (101). La mise en marche/l'arrêt d'un commutateur de vidage de mémoire (1023) sont commandés à l'aide d'un autre signal de commande parmi les signaux de commande des quatre phases dont la phase est différente de celle du signal de commande utilisé pour commander la mise en marche/l'arrêt du commutateur de charge (1021). Un condensateur tampon (1026) partage, par l'intermédiaire du commutateur de vidage de mémoire (1023), une charge avec le condensateur rotatif (1022), ce qui permet de former une valeur de sortie.
(JA)
 比較的簡易な構成及び簡易なクロックで、良好な周波数特性を有するダイレクトサンプリング回路及び受信機を開示する。離散時間回路(102-1~102-4)において、充電スイッチ(1021)は、4相の制御信号のうち、いずれか一つの制御信号を用いてオンオフ制御される。ローテートキャパシタ(1022)は、充電スイッチ(1021)を介して、IQ生成回路(101)に蓄積された電荷を電荷共有する。ダンプスイッチ(1023)は、4相の制御信号のうち、充電スイッチ(1021)をオンオフ制御する制御信号と位相が異なる信号が用いられてオンオフ制御される。バッファキャパシタ(1026)は、ダンプスイッチ(1023)を介して、ローテートキャパシタ(1022)と電荷共有することにより出力値を形成する。
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