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Machine translation
1. (WO2011021359) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/021359    International Application No.:    PCT/JP2010/004968
Publication Date: 24.02.2011 International Filing Date: 06.08.2010
IPC:
H03K 19/0175 (2006.01)
Applicants: PANASONIC CORPORATION [JP/JP]; 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501 (JP) (For All Designated States Except US).
NAKAMURA, Naoki; (For US Only).
OHTSUKA, Hidefumi; (For US Only)
Inventors: NAKAMURA, Naoki; .
OHTSUKA, Hidefumi;
Agent: MAEDA, Hiroshi; Osaka-Marubeni Bldg.,5-7,Hommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410053 (JP)
Priority Data:
2009-189406 18.08.2009 JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract: front page image
(EN)Disclosed is a semiconductor device wherein variance of output impedances of a plurality of output circuits is suppressed. The semiconductor device has the output circuits, and a calibration circuit which generates calibration signals for setting the output impedances of the output circuits to a reference value. Each of the output circuits has a correcting circuit which corrects the calibration signals, and an output buffer which sets the output impedance of the output circuit to a value that corresponds to the calibration signals corrected by means of the correcting circuit.
(FR)L'invention porte sur un dispositif semi-conducteur dans lequel on supprime la variation des impédances de sortie d'une pluralité de circuits de sortie. Le dispositif semi-conducteur comporte des circuits de sortie et un circuit d'étalonnage générant des signaux d'étalonnage destinés à configurer les impédances de sortie des circuits de sortie selon une valeur de référence. Chacun des circuits de sortie comprend un circuit de correction corrigeant les signaux d'étalonnage et une mémoire tampon de sortie configurant l'impédance de sortie du circuit de sortie selon une valeur correspondant aux signaux d'étalonnage corrigés au moyen du circuit de correction.
(JA) 複数の出力回路の出力インピーダンスのバラツキを抑える。半導体装置であって、複数の出力回路と、前記複数の出力回路の出力インピーダンスを基準値に設定するためのキャリブレーション信号を生成するキャリブレーション回路とを有する。前記複数の出力回路は、それぞれ、前記キャリブレーション信号を補正する補正回路と、その出力インピーダンスを前記補正回路で補正された前記キャリブレーション信号に応じた値にする出力バッファとを有する。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)