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Machine translation
1. (WO2011014158) METHOD AND SYSTEM FOR POWER-EFFICIENT AND NON-SIGNAL-DEGRADING VOLTAGE REGULATION IN MEMORY SUBSYSTEMS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/014158    International Application No.:    PCT/US2009/051875
Publication Date: 03.02.2011 International Filing Date: 27.07.2009
IPC:
G06F 1/26 (2006.01), G06F 1/32 (2006.01), G06F 13/16 (2006.01), G06F 13/14 (2006.01), G06F 12/00 (2006.01)
Applicants: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. [US/US]; 11445 Compaq Center Drive West Houston, TX 77070 (US) (For All Designated States Except US).
BACCHUS, Reza, M. [US/US]; (US) (For US Only).
NGUYEN, Vincent [US/US]; (US) (For US Only).
BENEDICT, Melvin, K. [US/US]; (US) (For US Only)
Inventors: BACCHUS, Reza, M.; (US).
NGUYEN, Vincent; (US).
BENEDICT, Melvin, K.; (US)
Agent: WEBB, Steven, L.; Hewlett-packard Company Intellectual Property Adminstration P.O. Box 272400, M/S 35 Fort Collins, CO 80527-2400 (US)
Priority Data:
Title (EN) METHOD AND SYSTEM FOR POWER-EFFICIENT AND NON-SIGNAL-DEGRADING VOLTAGE REGULATION IN MEMORY SUBSYSTEMS
(FR) PROCÉDÉ ET SYSTÈME DE RÉGULATION DE TENSION POUR SOUS SYSTÈMES DE MÉMOIRE EFFICACES EN TERMES D'ÉLECTRICITÉ ET SANS DÉGRADATION DE SIGNAL
Abstract: front page image
(EN)Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.
(FR)Dans certains modes de réalisation, cette invention concerne un sous-système mémoire comprenant une unité de commande de mémoire, des modules mémoire multiples interconnectés avec l'unité de commande de mémoire par un ou plusieurs supports de communication, chaque module mémoire comprenant un substrat sur lequel sont montées des puces de mémoire multiples connectées électroniquement aux support de communication et un signal d'alimentation électrique transmis à deux régulateurs de tension ou plus depuis l'alimentation du système, ces régulateurs de tension générant deux signaux de puissance internes en direction de chacune des puces de mémoires. Dans un autre mode de réalisation, l'invention concerne un module mémoire comprenant un substrat sur lequel sont montés des puces de mémoire multiples ainsi que deux régulateurs de tension ou plus montés sur ledit substrat ou intégrés à ce dernier au stade de la fabrication.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)