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1. (WO2011013596) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2011/013596    International Application No.:    PCT/JP2010/062484
Publication Date: 03.02.2011 International Filing Date: 20.07.2010
IPC:
H01L 29/786 (2006.01)
Applicants: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 398, Hase, Atsugi-shi, Kanagawa 2430036 (JP) (For All Designated States Except US).
YAMAZAKI, Shunpei [JP/JP]; (JP) (For US Only).
AKIMOTO, Kengo; (For US Only).
TSUBUKU, Masashi; (For US Only).
SASAKI, Toshinari; (For US Only).
KUWABARA, Hideaki; (For US Only)
Inventors: YAMAZAKI, Shunpei; (JP).
AKIMOTO, Kengo; .
TSUBUKU, Masashi; .
SASAKI, Toshinari; .
KUWABARA, Hideaki;
Priority Data:
2009-179722 31.07.2009 JP
Title (EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
Abstract: front page image
(EN)In a bottom-gate thin film transistor using the stack of the first oxide semiconductor layer and the second oxide semiconductor layer, an oxide insulating layer serving as a channel protective layer is formed over and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the insulating layer, an oxide insulating layer covering a peripheral portion (including a side surface) of the stack of the oxide semiconductor layers is formed.
(FR)Dans un transistor à couches minces à grille inférieure utilisant la pile de la première couche semi-conductrice d'oxyde et de la seconde couche semi-conductrice d'oxyde, une couche isolante d'oxyde tenant lieu de couche de protection de canal est formée au-dessus d'une partie de la couche semi-conductrice d'oxyde se chevauchant avec une couche d'électrode de grille et de manière à être en contact avec cette partie. Lors de la même étape de formation de la couche isolante, une couche isolante d'oxyde recouvrant une partie périphérique (incluant une surface latérale) de la pile des couches semi-conductrices d'oxyde est formée.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)