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1. (WO2011013417) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2011/013417 International Application No.: PCT/JP2010/057049
Publication Date: 03.02.2011 International Filing Date: 21.04.2010
IPC:
H01L 29/786 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants: NAKATANI, Yoshiki; null (UsOnly)
MORIGUCHI, Masao; null (UsOnly)
KANZAKI, Yohsuke; null (UsOnly)
TAKANISHI, Yudai; null (UsOnly)
SHARP KABUSHIKI KAISHA[JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
Inventors: NAKATANI, Yoshiki; null
MORIGUCHI, Masao; null
KANZAKI, Yohsuke; null
TAKANISHI, Yudai; null
Agent: SHIMADA, Akihiro; Shimada Patent Firm, Manseian Building, 1-10-3, Yagi-cho, Kashihara-shi, Nara 6340078, JP
Priority Data:
2009-17742630.07.2009JP
Title (EN) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME
(FR) TRANSISTOR À COUCHES MINCES ET PROCÉDÉ DE FABRICATION DE CELUI-CI
(JA) 薄膜トランジスタおよびその製造方法
Abstract:
(EN) Disclosed is a thin film transistor wherein the off-current of the thin film transistor is reduced, while maintaining the on-current of the thin film transistor. In the TFT (100), a source electrode (110) and a drain electrode (112) are formed on a glass substrate (101), and n-type silicon layers (120, 121) composed of fine crystalline silicon are formed on the upper surfaces of the electrodes. On the n-type silicon layers (120, 121), fine crystalline silicon regions (135, 136) are formed, and on the glass substrate (101), an amorphous silicon region (130) is formed. A fine crystalline silicon layer (145) is formed so as to cover the fine crystalline silicon regions and the amorphous silicon region. Therefore, the on-current flows from the drain electrode (112) to the source electrode (110) by flowing through the fine crystalline silicon region (135), the fine crystalline silicon layer (145), and the fine crystalline silicon region (136) in this order. Furthermore, the off-current is limited by means of the amorphous silicon region (130).
(FR) L'invention concerne un transistor à couches minces dans lequel le courant d'arrêt du transistor à couches minces est réduit pendant que le courant de marche est maintenu. Dans le TFT (100), une électrode source (110) et une électrode drain (112) sont formées sur un substrat de verre (101), et des couches de silicium (120, 121) de type n constituées de silicium cristallin fin sont formées sur les surfaces supérieures des électrodes. Sur les couches de silicium (120, 121) de type n, des régions (135, 136) de silicium cristallin fin sont formées, et sur le substrat de verre (101), une région (130) de silicium amorphe est formée. Une couche (145) de silicium cristallin fin est formée de manière à couvrir les régions de silicium cristallin fin et la région de silicium amorphe. Par conséquent, le courant de marche s'écoule de l'électrode drain (112) vers l'électrode source (110) en traversant la région (135) de silicium cristallin fin, la couche (145) de silicium cristallin fin et la région (136) de silicium cristallin fin, dans cet ordre. De plus, le courant d'arrêt est limité au moyen de la région (130) de silicium amorphe.
(JA)  本発明は、薄膜トランジスタのオン電流を維持しつつ、オフ電流を小さくすることを目的とする。 TFT(100)では、ガラス基板(101)上にソース電極(110)とドレイン電極(112)が形成され、それらの上面にはそれぞれ微結晶シリコンからなるn型シリコン層(120、121)が形成されている。n型シリコン層(120、121)上には微結晶シリコン領域(135、136)が形成され、ガラス基板(101)上には非晶質シリコン領域(130)が形成されている。それらを覆うように、微結晶シリコン層(145)が形成されている。したがって、オン電流は、ドレイン電極(112)から、微結晶シリコン領域(135)、微結晶シリコン層(145)、微結晶シリコン領域(136)の順に通って、ソース電極(110)に流れる。また、オフ電流は、非晶質シリコン領域(130)によって制限される。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)