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1. WO2011011769 - I/O MEMORY MANAGEMENT UNIT INCLUDING MULTILEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD

Publication Number WO/2011/011769
Publication Date 27.01.2011
International Application No. PCT/US2010/043169
International Filing Date 24.07.2010
IPC
G06F 12/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
CPC
G06F 12/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
G06F 12/1009
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1009using page tables, e.g. page table structures
G06F 12/1027
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1027using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1036
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1027using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
1036for multiple virtual address spaces, e.g. segmentation
G06F 12/1081
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1081for peripheral access to main memory, e.g. direct memory access [DMA]
G06F 2212/151
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
15Use in a specific computing environment
151Emulated environment, e.g. virtual machine
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US] (AllExceptUS)
  • KEGEL, Andrew, G. [US]/[US] (UsOnly)
  • HUMMEL, Mark, D. [US]/[US] (UsOnly)
Inventors
  • KEGEL, Andrew, G.
  • HUMMEL, Mark, D.
Agents
  • MEYERTONS, HOOD, KIVLIN, KOWERT & GOETZEL, P.C.
Priority Data
12/508,88224.07.2009US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) I/O MEMORY MANAGEMENT UNIT INCLUDING MULTILEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD
(FR) UNITÉ DE GESTION DE MÉMOIRE D'ENTRÉE/SORTIE COMPRENANT UNE TRANSFORMATION D'ADRESSE À MULTIPLES NIVEAUX POUR UNE ENTRÉE/SORTIE ET UN TRANSFERT DE CHARGE DE CALCUL
Abstract
(EN)
An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables. The selected device table entry for the given request may include a pointer to the set of guest translation tables, and a last guest translation table includes a pointer to the set of nested page tables
(FR)
Une unité de gestion de mémoire d'entrée/sortie (IOMMU) configurée pour commander des demandes effectuées par un dispositif d'entrée/sortie pour une mémoire de système comprend une logique de commande qui peut effectuer une transformation d'hôte à deux niveaux pour transformer une adresse associée à une demande générée par un dispositif d'entrée/sortie à l'aide de données de transformation mémorisées dans la mémoire de système. Les données de transformation comprennent une table de dispositif ayant un certain nombre d'entrées. La logique de commande peut sélectionner l'entrée de table de dispositif pour une demande donnée à l'aide d'un identifiant de dispositif qui correspond au dispositif d'entrée/sortie qui génère la demande. Les données de transformation peuvent également comprendre un premier ensemble de tables de pages d'entrée/sortie comprenant un ensemble de tables de pages d'hôte et un ensemble de tables de pages imbriquées. L'entrée de table de dispositif sélectionnée pour la demande donnée peut comprendre un pointeur vers l'ensemble de tables de transformation d'hôte, et une dernière table de transformation d'hôte comprend un pointeur vers l'ensemble de tables de pages imbriquées.
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