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1. WO2011010415 - METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

Publication Number WO/2011/010415
Publication Date 27.01.2011
International Application No. PCT/JP2010/001878
International Filing Date 16.03.2010
IPC
G09F 9/00 2006.01
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G02F 1/1368 2006.01
GPHYSICS
02OPTICS
FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01for the control of the intensity, phase, polarisation or colour
13based on liquid crystals, e.g. single liquid crystal display cells
133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362Active matrix addressed cells
1368in which the switching element is a three-electrode device
G09F 9/30 2006.01
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30in which the desired character or characters are formed by combining individual elements
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 29/786 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
CPC
G02F 1/1368
GPHYSICS
02OPTICS
FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
01for the control of the intensity, phase, polarisation or colour 
13based on liquid crystals, e.g. single liquid crystal display cells
133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362Active matrix addressed cells
1368in which the switching element is a three-electrode device
H01L 27/1225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1222with a particular composition, shape or crystalline structure of the active layer
1225with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
H01L 27/124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
124with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
H01L 27/1248
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1248with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
H01L 29/42384
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42384for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
H01L 29/7869
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
786Thin film transistors, ; i.e. transistors with a channel being at least partly a thin film
7869having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Applicants
  • シャープ株式会社 SHARP KABUSHIKI KAISHA [JP]/[JP] (AllExceptUS)
  • 岡部達 OKABE, Tohru (UsOnly)
  • 錦博彦 NISHIKI, Hirohiko (UsOnly)
  • 近間義雅 CHIKAMA, Yoshimasa (UsOnly)
  • 原猛 HARA, Takeshi (UsOnly)
Inventors
  • 岡部達 OKABE, Tohru
  • 錦博彦 NISHIKI, Hirohiko
  • 近間義雅 CHIKAMA, Yoshimasa
  • 原猛 HARA, Takeshi
Agents
  • 前田弘 MAEDA, Hiroshi
Priority Data
2009-17316024.07.2009JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION D'UN SUBSTRAT DE TRANSISTOR À COUCHES MINCES
(JA) 薄膜トランジスタ基板の製造方法
Abstract
(EN)
A method for manufacturing a thin film transistor substrate is provided with: a step of forming a gate electrode (11a) and first wiring on a substrate (10); a step of forming a gate insulating film (12a), which has a contact hole at a position overlapping the first wiring; a step of forming a source electrode (13a) and a drain electrode (13b), which are provided such that the electrodes overlap the gate electrode (11a) and that the electrodes are being spaced apart from each other, and forming second wiring, which is connected to the first wiring via the contact hole in the gate insulating film (12a); a step of forming an interlayer insulating film (15a) by patterning the second insulating film (15) after sequentially forming an oxide semiconductor film (14) and the second insulating film (15); and a step of forming a pixel electrode (14b) by making the oxide semiconductor film (14) exposed from the interlayer insulating film (15a) have a low resistivity.
(FR)
La présente invention concerne un procédé de fabrication d'un substrat de transistor à couches minces comportant : une étape consistant à former une électrode de grille (11a) et un premier câblage sur un substrat (10) ; une étape consistant à former un film d'isolation de grille (12a) qui a un trou de contact à une position recouvrant partiellement le premier câblage ; une étape consistant à former une électrode de source (13a) et une électrode de drain (13b) qui sont disposées de sorte que les électrodes recouvrent partiellement l'électrode de grille (11a) et de sorte que les électrodes soient espacées les unes des autres, et à former un deuxième câblage qui est connecté au premier câblage via le trou de contact dans le film d'isolation de grille (12a) ; une étape consistant à former un film d'isolation entre les couches (15a) en réalisant des motifs sur le second film d'isolation (15) après avoir formé successivement un film semi-conducteur d'oxyde (14) et le second film d'isolation (15) ; et une étape consistant à former une électrode de pixel (14b) en faisant en sorte que le film semi-conducteur d'oxyde (14) exposé depuis le film d'isolation entre les couches (15a) ait une faible résistivité.
(JA)
 基板(10)にゲート電極(11a)及び第1の配線を形成する工程と、第1の配線に重なる位置にコンタクトホールを有するゲート絶縁膜(12a)を形成する工程と、ゲート電極(11a)に重なると共に互いに離間するようにそれぞれ設けられたソース電極(13a)及びドレイン電極(13b)と、第1の配線にゲート絶縁膜(12a)のコンタクトホールを介して接続された第2の配線とを形成する工程と、酸化物半導体膜(14)及び第2の絶縁膜(15)を順に成膜した後に、第2の絶縁膜(15)をパターニングして層間絶縁膜(15a)を形成する工程と、層間絶縁膜(15a)から露出する酸化物半導体膜(14)を低抵抗化して画素電極(14b)を形成する工程とを備える。
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