Processing

Please wait...

PATENTSCOPE will be unavailable a few hours for maintenance reason on Saturday 31.10.2020 at 7:00 AM CET
Settings

Settings

Goto Application

1. WO2011002709 - COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR TESTER INTERFACE

Publication Number WO/2011/002709
Publication Date 06.01.2011
International Application No. PCT/US2010/040188
International Filing Date 28.06.2010
IPC
G01R 31/26 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26Testing of individual semiconductor devices
CPC
G01R 1/0466
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
1Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
02General constructional details
04Housings; Supporting members; Arrangements of terminals
0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
0433Sockets for IC's or transistors
0441Details
0466concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
G01R 1/07314
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
1Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
02General constructional details
06Measuring leads; Measuring probes
067Measuring probes
073Multiple probes
07307with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
07314the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
G01R 1/0735
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
1Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
02General constructional details
06Measuring leads; Measuring probes
067Measuring probes
073Multiple probes
07307with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
0735arranged on a flexible frame or film
G01R 1/07378
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
1Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
02General constructional details
06Measuring leads; Measuring probes
067Measuring probes
073Multiple probes
07307with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
07364with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
07378using an intermediate adapter, e.g. space transformers
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
Y10T 29/49155
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
10TECHNICAL SUBJECTS COVERED BY FORMER USPC
TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
29Metal working
49Method of mechanical manufacture
49002Electrical device making
49117Conductor or circuit manufacturing
49124On flat or curved insulated base, e.g., printed circuit, etc.
49155Manufacturing circuit on or in base
Applicants
  • HSIO TECHNOLOGIES, LLC [US]/[US] (AllExceptUS)
  • RATHBURN, James [US]/[US] (UsOnly)
Inventors
  • RATHBURN, James
Agents
  • SCHWAPPACH, Karl, G.
Priority Data
61/221,35629.06.2009US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR TESTER INTERFACE
(FR) INTERFACE DE TESTEUR DE SEMI-CONDUCTEUR DE CIRCUIT IMPRIMÉ CONFORME
Abstract
(EN)
A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.
(FR)
L'invention concerne une interface de testeur de semi-conducteur de circuit imprimé conforme qui permet une interconnexion temporaire entre les bornes de dispositifs à circuit intégré (IC) à tester. L'interface de testeur de semi-conducteur de circuit imprimé conforme comporte au moins une couche de diélectrique imprimée avec des renfoncements correspondant à la géométrie d'un circuit cible. Un matériau conducteur est déposé dans au moins une partie des renforcements comprenant la géométrie d'un circuit et une pluralité de premiers plots de contact accessibles le long d'une première surface du circuit imprimé conforme. De préférence, au moins un revêtement diélectrique est appliqué sur la géométrie du circuit. Plusieurs ouvertures sont formées dans le revêtement diélectrique pour permettre un couplage électrique entre les bornes se trouvant sur le dispositif IC et les premiers plots de contact. L'électronique de test servant à tester les fonctions électriques du dispositif IC est couplée électriquement à la géométrie du circuit.
Also published as
Latest bibliographic data on file with the International Bureau