WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2010151891) PREDETERMINED DUTY CYCLE SIGNAL GENERATOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/151891    International Application No.:    PCT/US2010/040249
Publication Date: 29.12.2010 International Filing Date: 28.06.2010
IPC:
H03K 5/156 (2006.01), H03K 3/015 (2006.01), H03K 3/017 (2006.01), H03K 7/06 (2006.01), H03K 7/08 (2006.01), H03K 23/00 (2006.01)
Applicants: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121 (US) (For All Designated States Except US).
ZHANG, Kun [CN/US]; (US) (For US Only).
BARNETT, Kenneth Charles [US/US]; (US) (For US Only)
Inventors: ZHANG, Kun; (US).
BARNETT, Kenneth Charles; (US)
Agent: XU, Jiayu; Attn: International IP Administration 5775 Morehouse Drive San Diego, Califonia 92121 (US)
Priority Data:
61/220,831 26.06.2009 US
12/558,278 11.09.2009 US
Title (EN) PREDETERMINED DUTY CYCLE SIGNAL GENERATOR
(FR) GÉNÉRATEUR DE SIGNAL DE CYCLE DE CHARGE PRÉDÉTERMINÉ
Abstract: front page image
(EN)Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number.
(FR)L'invention concerne les techniques pour générer un signal ayant un cycle de charge prédéterminé. Dans un mode de réalisation exemplaire, un premier compteur est configuré pour compter un premier nombre de cycles d'un signal d'oscillateur, et un second compteur est configuré pour compter un second nombre de cycles du signal d'oscillateur, le second nombre étant supérieur au premier nombre. La sortie du second compteur est utilisée pour réinitialiser le premier et le second compteur, alors que les sorties du premier et du second compteur commandent également un mécanisme articulé pour générer le signal ayant un cycle de charge prédéterminé. Les autres aspects concernent les techniques pour accepter les valeurs paires et impaires pour le second nombre.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)