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Pub. No.:    WO/2010/151506    International Application No.:    PCT/US2010/039330
Publication Date: 29.12.2010 International Filing Date: 21.06.2010
H01L 23/48 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, NY 10504 (US) (For All Designated States Except US).
INTERRANTE, Mario, John [US/US]; (US) (For US Only).
DANOVITCH, David, Hirsch [CA/CA]; (CA) (For US Only).
SHAPIRO, Michael, Jay [US/US]; (US) (For US Only).
KNICKERBOCKER, John, Ulrich [US/US]; (US) (For US Only).
DANG, Bing [CN/US]; (US) (For US Only).
TRUONG, Van, Thanh [CA/CA]; (CA) (For US Only)
Inventors: INTERRANTE, Mario, John; (US).
DANOVITCH, David, Hirsch; (CA).
SHAPIRO, Michael, Jay; (US).
KNICKERBOCKER, John, Ulrich; (US).
DANG, Bing; (US).
TRUONG, Van, Thanh; (CA)
Agent: LEWIS, William, E.; Ryan, Mason & Lewis, Llp 90 Forest Avenue Locust Valley, NY 11560 (US)
Priority Data:
12/490,804 24.06.2009 US
Abstract: front page image
(EN)Methods and apparatus for forming an integrated circuit assembly are presented, for example, three dimensional integrated circuit assemblies. The use of, for example, thinned wafers, low-height solder bumps, and through silicon vias provide for low height three dimensional integrated circuit assemblies. For example, a method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum.
(FR)L'invention porte sur des procédés et un appareil de formation d'un ensemble circuit intégré, par exemple des ensembles circuits intégrés tridimensionnels. L'utilisation, par exemple, de tranches amincies, de perles de soudure de faible hauteur et de trous d'interconnexion dans le silicium permet d'obtenir des ensembles circuit intégré tridimensionnels de faible hauteur. Par exemple, un procédé de formation d'un ensemble circuit intégré consiste à former de premières perles de soudure sur une première puce, et à former une première structure comprenant la première puce, les premières perles de soudure, un premier flux et un premier substrat. La première puce est placée sur le premier substrat. Les premières perles de soudure se trouvent entre la première puce et le premier substrat. Le premier flux tient la première puce sensiblement à plat et sur le premier substrat.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)