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1. (WO2010147028) METHOD FOR MANUFACTURING A PLURALITY OF SEMICONDUCTOR CHIPS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/147028    International Application No.:    PCT/JP2010/059697
Publication Date: 23.12.2010 International Filing Date: 08.06.2010
IPC:
H01L 21/301 (2006.01), H01L 21/336 (2006.01), H01L 29/739 (2006.01), H01L 29/78 (2006.01)
Applicants: MITSUMI ELECTRIC CO., LTD. [JP/JP]; 2-11-2, Tsurumaki, Tama-Shi, Tokyo 2068567 (JP) (For All Designated States Except US).
FUJIOKA, Yasuhide [JP/JP]; (JP) (For US Only).
KANNBARA, Kouji [JP/JP]; (JP) (For US Only).
KIKUCHI, Hiroaki [JP/JP]; (JP) (For US Only)
Inventors: FUJIOKA, Yasuhide; (JP).
KANNBARA, Kouji; (JP).
KIKUCHI, Hiroaki; (JP)
Agent: ITOH, Tadahiko; 32nd Floor, Yebisu Garden Place Tower, 20-3, Ebisu 4-Chome, Shibuya-Ku, Tokyo 1506032 (JP)
Priority Data:
2009-142917 16.06.2009 JP
Title (EN) METHOD FOR MANUFACTURING A PLURALITY OF SEMICONDUCTOR CHIPS
(FR) PROCÉDÉ POUR LA FABRICATION D'UNE PLURALITÉ DE PUCES SEMI-CONDUCTRICES
(JA) 複数の半導体チップを製造する方法
Abstract: front page image
(EN)Disclosed is a method for manufacturing a plurality of semiconductor chips using a semiconductor substrate which has a plurality of first regions and a plurality of second regions that are positioned between the first regions. The method includes: a) a step of forming, in the second regions, a plurality of thick board portions and a plurality of thin board portions which include the first regions, by partially etching the rear surfaces of the first regions; b) a step of processing the rear surfaces of the thin board portions, corresponding to the type of the semiconductor chips to be manufactured; and c) a step of cutting and separating the first regions one from the other by cutting the semiconductor substrate along the boundaries between both the sides of respective second regions and the first regions.
(FR)L'invention concerne un procédé pour la fabrication d'une pluralité de puces semi-conductrices utilisant un substrat semi-conducteur comportant une pluralité de premières régions et une pluralité de secondes régions positionnées entre les premières régions. Le procédé comprend les étapes suivantes : a) formation, dans les secondes régions, d'une pluralité de parties de plaque épaisse et d'une pluralité de parties de plaque mince comprenant les premières régions, en gravant partiellement les surfaces arrière des premières régions; b) traitement des surfaces arrière des parties de plaque mince, correspondant au type de puce semi-conductrice devant être fabriqué; et c) découpe et séparation des premières régions les unes des autres en découpant le substrat semi-conducteur le long des limites entre les deux côtés des secondes régions respectives et des premières régions.
(JA) 複数の第一領域と前記複数の第一領域の間に位置する複数の第二領域とを有する半導体基板を用いて複数の半導体チップを製造する方法であって、a) 前記複数の第一領域の裏面を部分的にエッチングすることで、前記複数の第二領域内に複数の厚板部と前記複数の第一領域を包含する複数の薄板部とを形成する工程、b) 製造される前記複数の半導体チップの種類に応じて、前記複数の薄板部の裏面を加工する工程、c) 前記複数の第二領域の各第二領域の両側の前記複数の第一領域との境界に沿って前記半導体基板を切断することで、前記複数の第一領域を切り離す工程と、を含むことを特徴とする複数の半導体チップを製造する方法。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)