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Machine translation
1. (WO2010146843) FLIP-FLOP, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND BLADE SERVER
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/146843    International Application No.:    PCT/JP2010/003983
Publication Date: 23.12.2010 International Filing Date: 16.06.2010
IPC:
H03K 3/037 (2006.01), H03K 3/356 (2006.01), H03K 5/04 (2006.01), H03K 19/003 (2006.01)
Applicants: HITACHI, LTD. [JP/JP]; 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008280 (JP) (For All Designated States Except US).
SHIMBO, Kenichi [JP/JP]; (JP) (For US Only).
TOBA, Tadanobu [JP/JP]; (JP) (For US Only).
HIRANO, Katsunori [JP/JP]; (JP) (For US Only)
Inventors: SHIMBO, Kenichi; (JP).
TOBA, Tadanobu; (JP).
HIRANO, Katsunori; (JP)
Agent: INOUE, Manabu; c/o HITACHI, Ltd., 6-1, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008220 (JP)
Priority Data:
2009-144882 18.06.2009 JP
Title (EN) FLIP-FLOP, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND BLADE SERVER
(FR) BASCULE BISTABLE, CIRCUIT SEMICONDUCTEUR INTÉGRÉ, DISPOSITIF À SEMICONDUCTEURS ET SERVEUR DE TYPE LAME
(JA) フリップフロップ、半導体集積回路、半導体デバイスおよびブレードサーバ
Abstract: front page image
(EN)Disclosed is a flip-flop, provided with a plurality of latch circuits with differing resistance to soft errors, and a clock distribution unit which feeds a clock to the plurality of latch circuits, wherein the plurality of latch circuits are at least two latch circuits comprising a first latch circuit and a second latch circuit with lower resistance to soft errors than the first latch circuit.
(FR)L'invention concerne une bascule bistable dotée d'une pluralité de circuits de verrouillage avec une résistance différente aux erreurs aléatoires et une unité de distribution d'horloge qui fournit un signal d'horloge à la pluralité de circuits de verrouillage. La pluralité de circuits de verrouillage est constituée d'au moins deux circuits de verrouillage comprenant un premier circuit de verrouillage et un second circuit de verrouillage avec une résistance inférieure aux erreurs aléatoires au premier circuit de verrouillage.
(JA) ソフトエラーに対する耐性の異なる複数のラッチ回路と、前記複数のラッチ回路にクロックを供給するクロック分配部と、を備えたフリップフロップであって、前記複数のラッチ回路は、第一のラッチ回路と、前記第一のラッチ回路よりもソフトエラーに対する耐性の低い第二のラッチ回路の少なくとも2つのラッチ回路であることを特徴とするフリップフロップ。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)