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Machine translation
1. (WO2010146743) SHIFT REGISTER AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/146743    International Application No.:    PCT/JP2010/001259
Publication Date: 23.12.2010 International Filing Date: 24.02.2010
IPC:
G11C 19/28 (2006.01), G09G 3/20 (2006.01), G09G 3/36 (2006.01), G11C 19/00 (2006.01)
Applicants: SHARP KABUSHIKI KAISHA [JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522 (JP) (For All Designated States Except US).
NAKAMIZO, Masahiko; (For US Only).
YONEMARU, Masashi; (For US Only).
IWASE, Yasuaki; (For US Only).
ISHII, Kenichi; (For US Only)
Inventors: NAKAMIZO, Masahiko; .
YONEMARU, Masashi; .
IWASE, Yasuaki; .
ISHII, Kenichi;
Agent: HARAKENZO WORLD PATENT & TRADEMARK; Daiwa Minamimorimachi Building, 2-6, Tenjinbashi 2-chome Kita, Kita-ku, Osaka-shi, Osaka 5300041 (JP)
Priority Data:
2009-142554 15.06.2009 JP
Title (EN) SHIFT REGISTER AND DISPLAY DEVICE
(FR) REGISTRE À DÉCALAGE ET DISPOSITIF D'AFFICHAGE
(JA) シフトレジスタおよび表示装置
Abstract: front page image
(EN)Disclosed are a shift register and a display device which make it possible to effectively suppress noise in the output of each stage, without an increase in the size of the circuitry. The stages (Xi) of a shift register include: a first output transistor (M5); a first capacitor (C1); an input gate (M1); a first switching element (M2); a second switching element (M3); a third switching element (M4); a fourth switching element (M6); and a fifth switching element (M10).
(FR)L'invention concerne un registre à décalage et un dispositif d'affichage qui rendent possible la suppression effective du bruit dans la sortie de chaque étage, sans augmentation de la taille de la circuiterie. Les étages (Xi) d'un registre à décalage comprennent : un premier transistor de sortie (M5) ; un premier condensateur (C1) ; une porte d'entrée (M1) ; un premier élément de commutation (M2) ; un deuxième élément de commutation (M3) ; un troisième élément de commutation (M4) ; un quatrième élément de commutation (M6) ; et un cinquième élément de commutation (M10).
(JA) 回路規模を増大させることなく、各ステージ出力のノイズを良好に抑制することのできるシフトレジスタおよび表示装置を実現する。シフトレジスタの各ステージ(Xi)は、第1の出力トランジスタ(M5)と、第1の容量(C1)と、入力ゲート(M1)と、第1のスイッチング素子(M2)と、第2のスイッチング素子(M3)と、第3のスイッチング素子(M4)と、第4のスイッチング素子(M6)と、第5のスイッチング素子(M10)とを備えている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)