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1. (WO2010144624) PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/144624 International Application No.: PCT/US2010/038041
Publication Date: 16.12.2010 International Filing Date: 09.06.2010
IPC:
G06F 13/40 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
40
Bus structure
Applicants:
GOOGLE INC. [US/US]; 1600 Amphitheatre Parkway Mountain View, California 94043, US (AllExceptUS)
FEROLITO, Philip Arnold [US/US]; US (UsOnly)
ROSENBAND, Daniel L. [US/US]; US (UsOnly)
WANG, David T. [US/US]; US (UsOnly)
SMITH, Michael John Sebastian [GB/US]; US (UsOnly)
Inventors:
FEROLITO, Philip Arnold; US
ROSENBAND, Daniel L.; US
WANG, David T.; US
SMITH, Michael John Sebastian; US
Agent:
BRANT, Dmitry; Fish & Richardson P.C. P.O. Box 1022 Minneapolis, Minnesota 55440-1022, US
Priority Data:
61/185,58509.06.2009US
Title (EN) PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES
(FR) PROGRAMMATION DE VALEURS DE RÉSISTANCE DE TERMINAISON DIMM
Abstract:
(EN) Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
(FR) L'invention concerne des systèmes, des procédés et un appareil, notamment des produits-programmes informatiques, pour fournir une résistance de terminaison dans un module de mémoire. Un appareil est obtenu, cet appareil comprenant une pluralité de circuits de mémoire ; un circuit d'interface opérationnel pour communiquer avec la pluralité de circuits de mémoire et avec un contrôleur de mémoire ; et une ligne de transmission couplant électriquement le circuit d'interface à un contrôleur de mémoire, le circuit d'interface étant opérationnel pour terminer la ligne de transmission avec une résistance de terminaison unique qui est sélectionnée en fonction d'une pluralité de commandes de définition de résistance reçue du contrôleur de mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2441007