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1. (WO2010140621) SEMICONDUCTOR LIGHT DETECTING ELEMENT AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/140621    International Application No.:    PCT/JP2010/059353
Publication Date: 09.12.2010 International Filing Date: 02.06.2010
IPC:
H01L 31/10 (2006.01)
Applicants: HAMAMATSU PHOTONICS K.K. [JP/JP]; 1126-1, Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 4358558 (JP) (For All Designated States Except US).
ISHIKAWA Yoshitaka [JP/JP]; (JP) (For US Only).
SAKAMOTO Akira [JP/JP]; (JP) (For US Only).
YAMAMURA Kazuhisa [JP/JP]; (JP) (For US Only).
KAWAI Satoshi [JP/JP]; (JP) (For US Only)
Inventors: ISHIKAWA Yoshitaka; (JP).
SAKAMOTO Akira; (JP).
YAMAMURA Kazuhisa; (JP).
KAWAI Satoshi; (JP)
Agent: HASEGAWA Yoshiki; SOEI PATENT AND LAW FIRM Marunouchi MY PLAZA (Meiji Yasuda Life Bldg.) 9th fl. 1-1, Marunouchi 2-chome Chiyoda-ku, Tokyo 1000005 (JP)
Priority Data:
2009-136387 05.06.2009 JP
Title (EN) SEMICONDUCTOR LIGHT DETECTING ELEMENT AND MANUFACTURING METHOD THEREFOR
(FR) ÉLÉMENT DÉTECTEUR DE LUMIÈRE À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体光検出素子及び半導体光検出素子の製造方法
Abstract: front page image
(EN)A photo diode (PD1) is provided with an n--type semiconductor substrate (1) having a p-n junction formed from a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type. The n--type semiconductor substrate (1) is configured with an accumulation layer (7) that is formed in the second main surface (1b) of the n--type semiconductor substrate (1) and irregular protrusions and recesses (10) that are formed in at least the parts of the first main surface (1a) and second main surface (1b) facing the p-n junction. The parts of the first main surface (1a) and the second main surface (1b) of the n--type semiconductor substrate (1) which face the p-n junction are optically exposed.
(FR)L'invention porte sur une photodiode (PD1) qui comprend un substrat semi-conducteur de type n- (1) ayant une jonction p-n formée à partir d'une région semi-conductrice d'un premier type de conductivité et d'une région semi-conductrice d'un second type de conductivité. Le substrat semi-conducteur de type n- (1) est configuré avec une couche d'accumulation (7) qui est formée dans la seconde surface principale (1b) du substrat semi-conducteur de type n- (1) et des saillies et renfoncements irréguliers (10) qui sont formés dans au moins les parties de la première surface principale (1a) et de la seconde surface principale (1b) qui font face à la jonction p-n. Les parties de la première surface principale (1a) et de la seconde surface principale (1b) du substrat semi-conducteur de type n- (1) qui font face à la jonction p-n sont optiquement exposées.
(JA) フォトダイオードPD1は、第1導電型の半導体領域と第2導電型の半導体領域とで形成されたpn接合を有するn型半導体基板1を備えている。n型半導体基板1には、n型半導体基板1の第2主面1b側にアキュムレーション層7が形成されていると共に、第1主面1a及び第2主面1bにおける少なくともpn接合に対向する領域に不規則な凹凸10が形成されている。n型半導体基板1の第1主面1a及び第2主面1bにおけるpn接合に対向する領域は、光学的に露出している。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)