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1. (WO2010128415) EXTENSION OF CONTACT PADS TO THE DIE EDGE WITH ELECTRICAL ISOLATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/128415 International Application No.: PCT/IB2010/051627
Publication Date: 11.11.2010 International Filing Date: 14.04.2010
IPC:
H01L 33/38 (2010.01) ,H01L 33/20 (2010.01) ,H01L 33/44 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
36
characterised by the electrodes
38
with a particular shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
20
with a particular shape, e.g. curved or truncated substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
44
characterised by the coatings, e.g. passivation layer or anti-reflective coating
Applicants:
PHILIPS LUMILEDS LIGHTING COMPANY, LLC [US/US]; 370 West Trimble Road San Jose, CA 95131-1008, US (AllExceptUS)
KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL (AllExceptUS)
MARGALITH, Tal [US/US]; US (UsOnly)
SCHIAFFINO, Stefano [US/US]; US (UsOnly)
CHOY, Henry Kwong-Hin [CA/US]; US (UsOnly)
Inventors:
MARGALITH, Tal; US
SCHIAFFINO, Stefano; US
CHOY, Henry Kwong-Hin; US
Agent:
BEKKERS, Joost, J.J.; High Tech Campus Building 44 NL-5656 AE Eindhoven, NL
Priority Data:
12/436,44206.05.2009US
Title (EN) EXTENSION OF CONTACT PADS TO THE DIE EDGE WITH ELECTRICAL ISOLATION
(FR) EXTENSION DE PLOTS DE CONNEXION JUSQU'AU BORD DE LA PUCE AVEC ISOLATION ÉLECTRIQUE
Abstract:
(EN) Light emitting diode (LED) dies are fabricated by forming LED layers including a first conductivity type layer, a light-emitting layer, and a second conductivity type layer. Trenches are formed in the LED layers that reach at least partially into the first conductivity type layer. Electrically insulation regions are formed in or next to at least portions of the first conductivity type layer along the die edges. A first conductivity bond pad layer is formed to electrically contact the first conductivity type layer and extend over the singulation streets between the LED dies. A second conductivity bond pad layer is formed to electrically contact the second conductivity type layer, and extend over the singulation streets between the LED dies and the electrically insulated portions of the first conductivity type layer. The LED dies are mounted to submounts and the LED dies are singulated along the singulation streets between the LED dies.
(FR) Les puces de diode électroluminescente (LED) sont fabriquées en formant des couches de LED incluant une couche d'un premier type de conductivité, une couche électroluminescente et une couche d'un second type de conductivité. Dans les couches de LED sont formées des tranchées qui parviennent au moins partiellement dans la couche du premier type de conductivité. Des zones d'isolation électrique sont formées dans des parties au moins de la couche du premier type de conductivité, ou à proximité de ces parties, le long des bords de la puce. Une couche de plots de connexion d'une première conductivité est formée pour entrer en contact électrique avec la couche du premier type de conductivité et s'étend sur les voies de séparation entre les puces de LED. Une couche de plots de connexion d'une seconde conductivité est formée pour entrer en contact électrique avec la couche du second type de conductivité et s'étend sur les voies de séparation entre les puces de LED et les parties électriquement isolées de la couche du premier type de conductivité. Les puces de LED sont montées sur des sous-supports et les puces de LED sont séparées le long des voies de séparation entre les puces de LED.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2427923JP2012526378CN102422447RU2011149475RU0002523777KR1020120017443
IN8633/CHENP/2011