WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2010123263) METHOD FOR MANUFACTURING A POLYCRYSTALLINE SILICON THIN FILM
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/123263 International Application No.: PCT/KR2010/002477
Publication Date: 28.10.2010 International Filing Date: 20.04.2010
IPC:
H01L 21/324 (2006.01) ,H01L 21/20 (2006.01)
Applicants: RO, Jae-Sang[KR/KR]; KR (UsOnly)
HONG, Won-Eui[KR/KR]; KR (UsOnly)
ENSILTECH CORPORATION[KR/KR]; 914-915, IT Castle 1-dong 550-1, Gasan-dong, Geumcheon-gu Seoul 153-768, KR (AllExceptUS)
Inventors: RO, Jae-Sang; KR
HONG, Won-Eui; KR
Agent: CHOI, Young-Bok; Suite 1810, Hwanghwa Bldg., 832-7 Yeoksam-dong, Gangnam-gu Seoul 135-936, KR
Priority Data:
10-2009-003479121.04.2009KR
Title (EN) METHOD FOR MANUFACTURING A POLYCRYSTALLINE SILICON THIN FILM
(FR) PROCÉDÉ DE FABRICATION D'UN FILM MINCE EN SILICIUM POLYCRISTALLIN
(KO) 다결정 실리콘 박막의 제조방법
Abstract: front page image
(EN) The present invention relates to a method for manufacturing a polycrystalline silicon thin film, which involves applying power to a conductive thin film to generate joule heat and to thus manufacture a polycrystalline silicon thin film, and which exhibits crystallization characteristics at a low voltage the same as those at a high voltage, and which reduces manufacturing times and manufacturing costs. The present invention provides a method for manufacturing a polycrystalline silicon thin film comprising forming a first insulation layer, an amorphous silicon thin film, a second insulation layer, and a conductive thin film on a substrate, and applying an electric field to the conductive thin film through the use of electrodes, and crystallizing the amorphous silicon thin film by the high temperature heat generated by applying an electric field to the conductive thin film, wherein said electrodes are located at the center and at both ends of a range to which the electric field is to be applied, and a predetermined voltage is applied to the electrode located at the center of the range, and the electric field is applied to the earthed electrodes located at both ends of the range.
(FR) La présente invention concerne un procédé de fabrication d'un film mince en silicium polycristallin, qui consiste à appliquer une puissance sur un film mince conducteur afin de générer de la chaleur par effet Joule. Le film mince en silicium polycristallin présente, à basse tension, des caractéristiques de cristallisation identiques à celles observées à haute tension, ce qui permet de réduire les temps et coûts de fabrication. L'invention concerne un procédé de fabrication d'un film mince en silicium polycristallin, qui consiste à former sur un substrat: une première couche isolante, un film mince en silicium amorphe, une seconde couche isolante et un film mince conducteur; à appliquer un champ électrique sur le film mince conducteur au moyen d'électrodes; et à cristalliser le film mince en silicium amorphe par la chaleur générée à température élevée par application d'un champ électrique sur le film mince conducteur. Lesdites électrodes sont situées au centre et aux deux extrémités d'une plage dans laquelle le champ électrique doit être appliqué; une tension prédéterminée est appliquée sur l'électrode située au centre de la plage; et le champ électrique est appliquée sur les électrodes mises à la masse situées aux deux extrémités de la plage.
(KO) 본 발명은 다결정 실리콘 박막의 제조방법에 관한 것으로, 도전성 박막에 전원을 인가함으로써 주울(jule) 열을 발생시키고, 이를 통하여 다결정 실리콘 박막을 제조함에 있어서, 낮은 전압에서도 높은 전압과 같은 동일한 결정화 특성을 낼 수 있으며, 제조시간 및 제조비용을 절감할 수 있는 다결정 실리콘 박막 제조방법에 관한 것이다. 본 발명은 기판 상에 제1 절연층, 비정질 실리콘 박막, 제2 절연층 및 도전성 박막을 순차적으로 형성하고, 전극을 이용하여 상기 도전성 박막에 전계를 인가하여 발생되는 고열에 의해 상기 비정질 실리콘 박막을 결정화하는 다결정 실리콘 박막의 제조방법에 있어서, 상기 전극은 전계를 인가하고자 하는 범위의 중심부 및 양 단부에 위치하고, 중심부에 위치하는 전극에는 소정의 전압이 인가되고, 양 단부에 위치하는 전극은 접지된 상태로 전계가 인가되는 것을 특징으로 하는 다결정 실리콘 박막의 제조방법을 제공한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)