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1. (WO2010122754) SEMICONDUCTOR INTEGRATED CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/122754 International Application No.: PCT/JP2010/002792
Publication Date: 28.10.2010 International Filing Date: 16.04.2010
IPC:
H01L 21/82 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/822 (2006.01) ,H01L 23/52 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants: NISHIMURA, Hidetoshi; null (UsOnly)
TAMARU, Masaki; null (UsOnly)
PANASONIC CORPORATION[JP/JP]; 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
Inventors: NISHIMURA, Hidetoshi; null
TAMARU, Masaki; null
Agent: MAEDA, Hiroshi; Osaka-Marubeni Bldg.,5-7,Hommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410053, JP
Priority Data:
2009-10426822.04.2009JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT
(FR) CIRCUIT INTÉGRÉ À SEMI-CONDUCTEURS
(JA) 半導体集積回路
Abstract:
(EN) Provided is a semiconductor integrated circuit wherein pMOS transistors (P101-P108) are formed on a substrate in the X axis direction such that the gate length direction of each of the transistors matches the X axis direction, and nMOS transistors (N101-N108) are formed on the substrate in the X axis direction such that each of the gate length directions of the transistors matches the X axis direction and faces each of the pMOS transistors (P101-P108) in the Y axis direction. Gate wiring lines (G101-G108) correspond to the pMOS transistors (P101-P108) and the nMOS transistors (N101-N108), respectively, and linearly extend in parallel to each other in the Y axis direction such that each of the gate wiring lines passes through the gate positions of the pMOS transistor and the nMOS transistor which correspond to each of the wiring lines.
(FR) L'invention porte sur un circuit intégré à semi-conducteur, dans lequel des transistors pMOS (P101-P108) sont formés sur un substrat dans la direction de l'axe X, de telle sorte que la direction longitudinale de la grille de chacun des transistors correspond à la direction de l'axe X, et dans lequel des transistors nMOS (N101-N108) sont formés sur le substrat dans la direction de l'axe X de telle sorte que chacune des directions longitudinales de la grille des transistors correspond à la direction de l'axe X et fait face à chacun des transistors pMOS (P101-P108) dans la direction de l'axe Y. Des conducteurs de câblage de grille (G101-G108) correspondent respectivement aux transistors pMOS (P101-P108) et aux transistors nMOS (N101-N108) et s'étendent linéairement en parallèle les uns avec les autres dans la direction de l'axe Y de telle sorte que chacun des conducteurs de câblage de grille passe par les positions de grille du transistor pMOS et du transistor nMOS qui correspond à chacune des lignes de câblage.
(JA)  pMOSトランジスタ(P101,…,P108)は、それぞれのゲート長方向がX軸方向に一致するように、X軸方向に沿って基板に形成される。nMOSトランジスタ(N101,…,N108)は、それぞれのゲート長方向がX軸方向に一致するように、X軸方向に沿って基板に形成され、Y軸方向においてpMOSトランジスタ(P101,…,P108)にそれぞれ対向する。ゲート配線(G101,…,G108)は、pMOSトランジスタ(P101,…,P108)およびnMOSトランジスタ(N101,…,N108)にそれぞれ対応し、それぞれが自己に対応するpMOSトランジスタおよびnMOSトランジスタのゲート位置を通過するように、Y軸方向に沿ってそれぞれ平行に直線的に延在する。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)