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1. (WO2010120704) POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH EMBEDDED DIELECTRIC LAYERS CONTAINING PERMANENT CHARGES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/120704 International Application No.: PCT/US2010/030790
Publication Date: 21.10.2010 International Filing Date: 12.04.2010
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
DARWISH, Mohamed, N. [US/US]; US (UsOnly)
ZENG, Jun [US/US]; US (UsOnly)
BLANCHARD, Richard, A. [US/US]; US (UsOnly)
MAXPOWER SEMICONDUCTOR INC. [US/US]; 4800 Great America Parkway Suite 205 Santa Clara, CA 95054, US (AllExceptUS)
Inventors:
DARWISH, Mohamed, N.; US
ZENG, Jun; US
BLANCHARD, Richard, A.; US
Agent:
GROOVER, Robert, O.; Box 802889 Dallas, TX 75380, US
Priority Data:
61/168,79413.04.2009US
Title (EN) POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH EMBEDDED DIELECTRIC LAYERS CONTAINING PERMANENT CHARGES
(FR) DISPOSITIFS À SEMI-CONDUCTEURS ÉLECTRIQUES, PROCÉDÉS, ET STRUCTURES À COUCHES DIÉLECTRIQUES INTÉGRÉES CONTENANT DES CHARGES PERMANENTES
Abstract:
(EN) Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.
(FR) L'invention concerne des dispositifs électriques utilisant des tranchées remplies avec une charge permanente sur leurs parois latérales ou près de celles-ci. Ces tranchées s'étendent verticalement dans une région de dérive.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)