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1. (WO2010120676) PROCESSOR WITH ASSIGNABLE GENERAL PURPOSE REGISTER SET
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/120676 International Application No.: PCT/US2010/030721
Publication Date: 21.10.2010 International Filing Date: 12.04.2010
IPC:
G06F 13/26 (2006.01)
Applicants: JUSTICE, Robert, Sean[US/US]; US (UsOnly)
BODDIE, Tyler, Nye[US/US]; US (UsOnly)
TRIECE, Joseph[US/US]; US (UsOnly)
MICROCHIP TECHNOLOGY INCORPORATED[US/US]; 2355 West Chandler Blvd. Chandler, AZ 85224-6199, US (AllExceptUS)
Inventors: JUSTICE, Robert, Sean; US
BODDIE, Tyler, Nye; US
TRIECE, Joseph; US
Agent: SLAYDEN, Bruce, W., II; King & Spalding LLP 401 Congress Ave., Suite 3200 Austin, TX 78701, US
Priority Data:
12/749,06529.03.2010US
61/168,69913.04.2009US
Title (EN) PROCESSOR WITH ASSIGNABLE GENERAL PURPOSE REGISTER SET
(FR) PROCESSEUR COMPRENANT UN ENSEMBLE DE REGISTRES GÉNÉRAUX AFFECTABLES
Abstract: front page image
(EN) A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.
(FR) L'invention concerne un processeur comprenant une unité centrale (UC), un premier ensemble de registres d'unité centrale, un second ensemble de registres d'unité centrale, une logique de multiplexage destinée à coupler le premier ou le second ensemble de registres d'unité centrale avec l'unité centrale, et une logique de commande destinée à commander la logique de multiplexage pour qu'elle commute du premier ensemble de registres d'unité centrale au second ensemble de registres d'unité centrale lors de la réception d'au moins un signal d'une pluralité de signaux d'interruption, le ou les signaux de la pluralité de signaux d'interruption devant satisfaire à une condition qui est programmable dans la logique de commande.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)