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1. (WO2010119792) SUBSTRATE, SUBSTRATE PROVIDED WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/119792    International Application No.:    PCT/JP2010/056206
Publication Date: 21.10.2010 International Filing Date: 06.04.2010
IPC:
C30B 29/36 (2006.01), C23C 16/32 (2006.01), C23C 16/42 (2006.01), C30B 25/20 (2006.01), H01L 21/02 (2006.01), H01L 21/205 (2006.01), H01L 21/329 (2006.01), H01L 21/336 (2006.01), H01L 21/337 (2006.01), H01L 21/338 (2006.01), H01L 29/12 (2006.01), H01L 29/47 (2006.01), H01L 29/78 (2006.01), H01L 29/80 (2006.01), H01L 29/808 (2006.01), H01L 29/812 (2006.01), H01L 29/861 (2006.01), H01L 29/872 (2006.01)
Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD. [JP/JP]; 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041 (JP) (For All Designated States Except US).
HARADA, Shin [JP/JP]; (JP) (For US Only).
SASAKI, Makoto [JP/JP]; (JP) (For US Only).
MASUDA, Takeyoshi [JP/JP]; (JP) (For US Only)
Inventors: HARADA, Shin; (JP).
SASAKI, Makoto; (JP).
MASUDA, Takeyoshi; (JP)
Agent: FUKAMI, Hisao; Fukami Patent Office, p.c., Nakanoshima Central Tower, 2-7, Nakanoshima 2-chome, Kita-ku, Osaka-shi, Osaka 5300005 (JP)
Priority Data:
2009-098793 15.04.2009 JP
Title (EN) SUBSTRATE, SUBSTRATE PROVIDED WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) SUBSTRAT, SUBSTRAT DOTÉ D'UN FILM MINCE, DISPOSITIF SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR
(JA) 基板、薄膜付き基板、半導体装置、および半導体装置の製造方法
Abstract: front page image
(EN)Provided are a substrate which suppresses deterioration of processing accuracy of a semiconductor device due to the warping of the substrate, a substrate provided with a thin film, a semiconductor device formed using the abovementioned substrate, and a method for manufacturing said semiconductor device. In the substrate (1), the diameter of the main surface (1a) is 2 inches or more, the bow value of the main surface (1a) is -40 μm to -5 μm, and the warp value of the main surface (1a) is 5 μm to 40 μm. The value of the surface roughness (Ra) of the main surface (1a) of the substrate (1) is preferably 1 nm or less and the value of the surface roughness (Ra) of the main surface (1b) is preferably 100 nm or less.
(FR)L'invention porte sur un substrat qui permet de diminuer la détérioration de la précision de traitement d'un dispositif semi-conducteur due au gauchissement d'un substrat ; sur un dispositif semi-conducteur formé à l'aide d'un substrat doté d'un film mince et du substrat mentionné ci-dessus ; et sur un procédé de fabrication d'un tel dispositif semi-conducteur. Dans le substrat (1), le diamètre de la surface principale (1a) est de 2 pouces ou plus, la valeur de courbure de la surface principale (1a) est de -40 μm to -5 μm, et la valeur de gauchissement de la surface principale (1a) est de 5 μm to 40 μm. La valeur de la rugosité de surface (Ra) de la surface principale (1a) du substrat (1) est, de préférence, de 1 nm ou moins, et la valeur de la rugosité de surface (Ra) de la surface principale (1b) est, de préférence, de 100 nm ou moins.
(JA) 基板の湾曲による半導体装置の加工精度の劣化を抑制する基板、薄膜付き基板および上記基板を用いて形成された半導体装置、さらに上記半導体装置の製造方法が得られる。本発明における基板(1)は、主表面(1a)の直径が2インチ以上であり、主表面(1a)におけるbowの値が-40μm以上-5μm以下、主表面(1a)におけるwarpの値が5μm以上40μm以下である。基板(1)の、主表面(1a)の表面粗さRaの値が1nm以下、主表面(1b)の表面粗さRaの値が100nm以下であることが好ましい。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)