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Machine translation
1. (WO2010117987) BUMPED, SELF-ISOLATED GAN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/117987    International Application No.:    PCT/US2010/030049
Publication Date: 14.10.2010 International Filing Date: 06.04.2010
IPC:
H01L 23/34 (2006.01)
Applicants: EFFICIENT POWER CONVERSION CORPORATION [US/US]; 909 N. Sepulveda Boulevard Suite 230 El Segundo, CA 90245 (US) (For All Designated States Except US).
LIDOW, Alexander [US/US]; (US) (For US Only).
BEACH, Robert [US/US]; (US) (For US Only).
NAKATA, Alana [US/US]; (US) (For US Only).
CAO, Jianjun [US/US]; (US) (For US Only)
Inventors: LIDOW, Alexander; (US).
BEACH, Robert; (US).
NAKATA, Alana; (US).
CAO, Jianjun; (US)
Agent: SOFFEN, Stephen, A.; Dickstein Shapiro LLP 1825 Eye Street, NW Washington, DC 20006-5403 (US)
Priority Data:
61/167,773 08.04.2009 US
Title (EN) BUMPED, SELF-ISOLATED GAN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE
(FR) PUCE DE TRANSISTOR GAN À BILLE AUTO-ISOLÉ À SURFACE ARRIÈRE ÉLECTRIQUEMENT ISOLÉE
Abstract: front page image
(EN)A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an A1N seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.
(FR)L'invention concerne un dispositif semi-conducteur comprenant un substrat de silicium, un matériau semi-conducteur composé, un matériau isolant entre le substrat de silicium et le matériau semi-conducteur composé, et une surface supérieure comprenant des moyens de connexion électrique et un matériau de passivation, dans lequel le matériau de passivation est du nitrure de silicium, du dioxyde de silicium, ou une combinaison des deux. La présente invention élimine le besoin d'un isolant électrique épais entre un dissipateur thermique et la surface arrière d'un dispositif pour montage en surface par l'inclusion d'une couche germe d'AlN pour isoler électriquement le substrat de silicium du dispositif. Les parois latérales du dispositif sont aussi électriquement isolées de la zone active du dispositif.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)