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1. (WO2010117586) INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/117586 International Application No.: PCT/US2010/027783
Publication Date: 14.10.2010 International Filing Date: 18.03.2010
Chapter 2 Demand Filed: 20.01.2011
IPC:
H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants: XILINX, INC.[US/US]; 2100 Logic Drive San Jose, CA 95124, US (AllExceptUS)
Inventors: SADOUGHI, Sharmin; US
Agent: LIU, Justin; Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124, US
Priority Data:
12/420,67208.04.2009US
Title (EN) INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ AVEC COUCHE DE RÉDUCTION DE LA CONTRAINTE
Abstract:
(EN) An integrated circuit device is disclosed that includes a dual stress liner NMOS device (110) having a tensile stress layer (141 ) that overlies a NMOS gate film stack (122), a dual stress liner PMOS device (111 ) having a compressive stress layer (142) that overlies a PMOS gate film stack (123), a reduced -stress dual stress liner NMOS device (112) having a stress reduction layer (131 a) that extends between the tensile stress layer (141 ) and the NMOS gate film stack (124), and a reduced -stress dual stress liner PMOS device (113) having a stress reduction layer (131 b) that extends between the compressive stress layer (142) and the PMOS gate film stack (125). In embodiments of the invention additional reduced-stress dual stress liner NMOS devices (114) and reduced -stress PMOS devices (115) are formed by altering the thickness and/or the material properties of the stress reduction layer (132a, 132b).
(FR) L'invention concerne un dispositif de circuit intégré qui comprend un dispositif NMOS avec couche de contrainte double (110) ayant une couche de contrainte de tension (141 ) qui recouvre un empilement de film de porte NMOS (122), un dispositif de couche de contrainte double PMOS (111) ayant une couche de contrainte compressive (142) qui recouvre un empilement de film de porte PMOS (123), un dispositif NMOS de couche de contrainte double à contrainte réduite (112) ayant une couche de réduction de contrainte (131 a) qui s'étend entre la couche de contrainte de tension (141) et l'empilement de film de porte NMOS (124), et un dispositif PMOS (113) de couche de contrainte double à contrainte réduite (113) ayant une couche de réduction de contrainte (131 b) qui s'étend entre la couche de contrainte compressive (142) et l'empilement de film de porte PMOS (125). Dans des modes de réalisation de l'invention, des dispositifs NMOS (114) à couche de contrainte double à contrainte réduite et des dispositifs PMOS (115) à contrainte réduite sont formés en modifiant l'épaisseur et/ou les propriétés matérielles de la couche de réduction de contrainte (132a, 132b).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)