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1. (WO2010116993) STRUCTURE HAVING INTEGRATED CIRCUIT MOUNTED THEREIN
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/116993 International Application No.: PCT/JP2010/056230
Publication Date: 14.10.2010 International Filing Date: 06.04.2010
IPC:
H05K 9/00 (2006.01) ,H01L 23/00 (2006.01) ,H01P 1/26 (2006.01) ,H05K 7/20 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
9
Screening of apparatus or components against electric or magnetic fields
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
P
WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE
1
Auxiliary devices
24
Terminating devices
26
Dissipative terminations
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
7
Constructional details common to different types of electric apparatus
20
Modifications to facilitate cooling, ventilating, or heating
Applicants:
提坂 洋 SAGESAKA, Hiroshi; null (UsOnly)
大久保 公則 OKUBO, Masanori; null (UsOnly)
久保田 英正 KUBOTA, Hidemasa; null (UsOnly)
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府大阪市阿倍野区長池町22番22号 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP (AllExceptUS)
Inventors:
提坂 洋 SAGESAKA, Hiroshi; null
大久保 公則 OKUBO, Masanori; null
久保田 英正 KUBOTA, Hidemasa; null
Agent:
深見 久郎 FUKAMI, Hisao; 大阪府大阪市北区中之島二丁目2番7号 中之島セントラルタワー22階 深見特許事務所 Fukami Patent Office, Nakanoshima Central Tower, 22nd Floor, 2-7, Nakanoshima 2-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
2009-09319207.04.2009JP
Title (EN) STRUCTURE HAVING INTEGRATED CIRCUIT MOUNTED THEREIN
(FR) STRUCTURE CONTENANT UN CIRCUIT INTÉGRÉ
(JA) 集積回路の搭載構造
Abstract:
(EN) Provided is a structure having an integrated circuit mounted therein, by which EMI in an electronic apparatus having the integrated circuit mounted on a printed board is reduced. A heat sink (2) is provided in contact with an integrated circuit package (7). A circuit element (5) having electric loss is provided between the heat sink (2) and second wiring (4).
(FR) La présente invention concerne une structure dans laquelle un circuit intégré a été monté, permettant de réduire les EMI (interférences électromagnétiques) dans un appareil électronique dans lequel le circuit électrique a été monté sur une carte de circuit imprimé. Un dissipateur thermique (2) est placé en contact avec un module de circuit intégré (7). Un élément circuit (5) ayant une perte électrique est placé entre le dissipateur thermique (2) et le second câblage (4).
(JA)  プリント基板上に搭載される集積回路を有する電子機器におけるEMIを低減させる事を目的とする。集積回路パッケージ(7)と当接するようにヒートシンク(2)が設けられる。ヒートシンク(2)と第2の配線(4)との間に電気的損失性を有する回路素子(5)が設けられる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)