Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2010116887) INSULATED GATE FIELD EFFECT TRANSISTOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/116887 International Application No.: PCT/JP2010/054951
Publication Date: 14.10.2010 International Filing Date: 23.03.2010
IPC:
H01L 29/78 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
原田 真 HARADA, Shin [JP/JP]; JP (UsOnly)
和田 圭司 WADA, Keiji [JP/JP]; JP (UsOnly)
日吉 透 HIYOSHI, Toru [JP/JP]; JP (UsOnly)
住友電気工業株式会社 SUMITOMO ELECTRIC INDUSTRIES, LTD. [JP/JP]; 大阪府大阪市中央区北浜四丁目5番33号 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP (AllExceptUS)
Inventors:
原田 真 HARADA, Shin; JP
和田 圭司 WADA, Keiji; JP
日吉 透 HIYOSHI, Toru; JP
Agent:
深見 久郎 FUKAMI, Hisao; 大阪府大阪市北区中之島二丁目2番7号  中之島セントラルタワー 特許業務法人深見特許事務所 Fukami Patent Office, p.c. Nakanoshima Central Tower 2-7, Nakanoshima 2-chome, Kita-ku Osaka-shi, Osaka 5300005, JP
Priority Data:
2009-09548210.04.2009JP
Title (EN) INSULATED GATE FIELD EFFECT TRANSISTOR
(FR) TRANSISTOR À EFFET DE CHAMP À GRILLE ISOLÉE
(JA) 絶縁ゲート型電界効果トランジスタ
Abstract:
(EN) Disclosed is a MOSFET (metal oxide semiconductor field effect transistor) (1) which is capable of reducing the on-resistance by decreasing the channel mobility even when the gate voltage is high. The MOSFET (1) comprises: an n-type substrate (11) that is composed of SiC and has a main surface having an off angle with respect to the {0001} plane of 50-65˚; an n-type withstand voltage maintaining layer (13) that is composed of SiC and formed on the main surface (11A) of the substrate (11); a p-type well region (14) that is formed in the withstand voltage maintaining layer (13) at a distance from a first main surface (13A); a gate oxide film (18) that is formed on the well region (14); an n-type contact region (15) that is arranged between the well region (14) and the gate oxide film (18); a channel region (17) that connects the n-type contact region (15) with the withstand voltage maintaining layer (13); and a gate electrode (20) that is arranged on the gate oxide film (18). In the MOSFET (1), a high nitrogen concentration region (23) is formed in a region that contains the interface between the channel region (17) and the gate oxide film (18).
(FR) L'invention concerne un transistor MOSFET (transistor à effet de champ à semi-conducteur à oxyde métallique) (1) capable de réduire la résistance à l'état passant en réduisant la mobilité du canal même lorsque la tension de grille est élevée. Le MOSFET (1) comprend : un substrat de type n (11) qui est composé de SiC et ayant une surface principale présentant un angle de dépointage par rapport au plan {0001} de 50 à 65°; une couche de maintien de la tension d'entretien de type n (13) qui est composée de SiC et est formée sur la surface principale (11A) du substrat (11); une région de puits de type p (14) qui est formée dans la couche de maintien de tension de tenue (13) à une certaine distance d'une première surface principale (13A); un film d'oxyde de grille (18) qui est formé sur la région de puits (14); une région de contact de type n (15) qui est disposée entre la région de puits (14) et le film d'oxyde de grille (18); une région de canal (17) qui connecte la région de contact de type n (15) à la couche de maintien de tension de tenue (13); et une électrode de grille (20) qui est disposée sur le film d'oxyde de grille (18). Dans le MOSFET (1), une région à haute concentration en azote (23) est formée dans une région qui contient l'interface entre la région de canal (17) et le film d'oxyde de grille (18).
(JA)  ゲート電圧が高い場合でも、チャネル移動度を低減することによりオン抵抗を低減することが可能なMOSFET(1)は、SiCからなり、{0001}面に対するオフ角が50°~65°の主面を有するn型の基板(11)と、SiCからなり、基板(11)の主面(11A)上に形成されたn型の耐圧保持層(13)と、耐圧保持層(13)において、第1の主面(13A)から離れて形成されたp型のウェル領域(14)と、ウェル領域(14)上に形成されたゲート酸化膜(18)と、ウェル領域(14)とゲート酸化膜(18)との間に配置されたn型コンタクト領域(15)と、n型コンタクト領域(15)と耐圧保持層(13)とを接続するチャネル領域(17)と、ゲート酸化膜(18)上に配置されたゲート電極(20)とを備えている。そして、チャネル領域(17)とゲート酸化膜(18)との界面を含む領域には、高窒素濃度領域(23)が形成されている。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)