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1. (WO2010116325) PACKAGE FOR A SEMICONDUCTOR DIE AND METHOD OF MAKING THE SAME.
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/116325 International Application No.: PCT/IB2010/051487
Publication Date: 14.10.2010 International Filing Date: 06.04.2010
IPC:
H01L 21/60 (2006.01) ,H01L 23/538 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Applicants:
PEELS, W.G.M [NL/NL]; GB (UsOnly)
LUGT, A. Van Der [NL/NL]; GB (UsOnly)
NXP B.V. [NL/NL]; High Tech Campus 60 NL-5656 AG Eindhoven, NL (AllExceptUS)
Inventors:
PEELS, W.G.M; GB
LUGT, A. Van Der; GB
Agent:
WILLIAMSON, Paul, L.; c/o NXP Semiconductors IP Department Betchworth House 57-65 Station Road Redhill Surrey RH1 1DL, GB
Priority Data:
09100231.108.04.2009EP
Title (EN) PACKAGE FOR A SEMICONDUCTOR DIE AND METHOD OF MAKING THE SAME.
(FR) BOÎTIER POUR PUCE DE SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) The present invention relates to a package (24) for a die (2, 4) comprising an intermediate product (2, 6, 8) used for producing the package (24), the intermediate product (2, 6, 8) comprising a lead frame (6) having at least one pre-defined position (2e) for the die (2, 4), characterized by a rim (18) for at least partly surrounding the at least one pre-defined position (2e). A method is also provided of applying solderable material to said pre-defined position, soldering the die to said pre-defined position on said laid frame, laminating insulating material (10) to said lead frame, the insulating material having a cavity at said pre-defined position to accommodate the die, laminating a foil (14,16) thereto and providing interconnects through said foil to electrodes (2c,d;4c, d) on said die and through the insulating material (10) to said lead frame (6).
(FR) La présente invention porte sur un boîtier (24) pour une puce (2, 4) comprenant un produit intermédiaire (2, 6, 8) utilisé pour produire le boîtier (24), le produit intermédiaire (2, 6, 8) comprenant une grille de connexion (6) ayant au moins une position prédéfinie (2e) pour la puce (2, 4), caractérisé par un pourtour (18) destiné à entourer au moins partiellement l'au moins une position prédéfinie (2e). L'invention porte également sur un procédé consistant à appliquer un matériau brasable à ladite position prédéfinie, braser la puce à ladite position prédéfinie sur ladite grille de connexion, stratifier un matériau isolant (10) sur ladite grille de connexion, le matériau isolant comportant une cavité au niveau de ladite position prédéfinie pour loger la puce, stratifier une feuille (14, 16) sur celui-ci et ménager des interconnexions à travers ladite feuille à des électrodes (2c, d; 4c, d) sur ladite puce et à travers le matériau isolant (10) à ladite grille de connexion (6).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)