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1. (WO2010115924) METHOD FOR MANUFACTURING A MEMORY ELEMENT COMPRISING A RESISTIVITY-SWITCHING NiO LAYER AND DEVICES OBTAINED THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/115924 International Application No.: PCT/EP2010/054589
Publication Date: 14.10.2010 International Filing Date: 07.04.2010
IPC:
H01L 45/00 (2006.01) ,H01L 27/24 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24
including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Applicants:
LISONI REYES, Judit [CL/BE]; BE (UsOnly)
GOUX, Ludovic [FR/BE]; BE (UsOnly)
WOUTERS, Dirk [BE/BE]; BE (UsOnly)
IMEC [BE/BE]; Kapeldreef 75 B-3001 Leuven, BE (AllExceptUS)
Inventors:
LISONI REYES, Judit; BE
GOUX, Ludovic; BE
WOUTERS, Dirk; BE
Agent:
HERTOGHE, Kris; DenK iP bvba Hundelgemsesteenweg 1114 B-9820 Merelbeke, BE
Priority Data:
09157797.310.04.2009EP
09165515.915.07.2009EP
Title (EN) METHOD FOR MANUFACTURING A MEMORY ELEMENT COMPRISING A RESISTIVITY-SWITCHING NiO LAYER AND DEVICES OBTAINED THEREOF
(FR) PROCÉDÉ DE FABRICATION D'UN ÉLÉMENT DE MÉMOIRE COMPRENANT UNE COUCHE NIO À COMMUTATION DE RÉSISTIVITÉ ET DISPOSITIFS OBTENUS PAR CE PROCÉDÉ
Abstract:
(EN) The present invention provides a method for forming a NiO resistive memory element comprising a NiO resistive switching layer (31). The method comprises obtaining a substrate (34), providing a Ni layer on the substrate, and at least partially oxidizing the Ni layer, thus forming the NiO resistive switching layer (31), wherein obtaining a substrate comprises obtaining a substrate which promotes subsequent formation of Ni grains with slower oxidizing crystal orientations, e.g. (111) orientations, and/or suppresses formation of Ni grains with faster oxidizing crystal orientations, e.g. (100) orientations. This may be obtained, for example, bu providing on the substrate, a N-rich, Ti-poor TiN bottom electrode layer. By providing a substrate which promotes subsequent formation of Ni grains with slower oxidizing crystal orientations and/or suppresses formation of Ni grains with faster oxidizing crystal orientations, resistive memory elements with good switching properties may be formed.
(FR) La présente invention porte sur un procédé de formation d'un élément de mémoire résistif NiO comprenant une couche de commutation résistive NiO (31). Le procédé consiste à obtenir un substrat (34), produire une couche Ni sur le substrat, et oxyder au moins partiellement la couche Ni, pour ainsi former la couche de commutation résistive NiO (31), l'obtention d'un substrat comprenant l'obtention d'un substrat qui favorise une formation subséquente de grains Ni à orientations cristallines s'oxydant plus lentement, par exemple des orientations (111), et/ou supprime la formation de grains Ni ayant des orientations cristallines à oxydation plus rapide, par exemple des orientations (100). Cela peut être obtenu, par exemple, par production sur le substrat d'une couche d'électrode inférieure TiN riche en N et pauvre en Ti. Par utilisation d'un substrat qui favorise une formation subséquente de grains Ni ayant des orientations cristallines à oxydation plus lente et/ou supprime la formation de grains Ni ayant des orientations cristallines à oxydation plus rapide, des éléments de mémoire résistifs ayant de bonnes propriétés de commutation peuvent être formés.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)