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Machine translation
1. (WO2010114662) A THREE DIMENSIONAL INTERCONNECT STRUCTURE AND METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/114662    International Application No.:    PCT/US2010/025987
Publication Date: 07.10.2010 International Filing Date: 03.03.2010
IPC:
H05K 7/06 (2006.01)
Applicants: RESEARCH TRIANGLE INSTITUTE [US/US]; 3040 Cornwallis Road Research Triangle Park, NC 27709 (US) (For All Designated States Except US).
WILLIAMS, Charles, Kenneth [US/US]; (US) (For US Only).
BOWER, Christopher, A. [US/US]; (US) (For US Only).
MALTA, Dean, Michael [US/US]; (US) (For US Only).
TEMPLE, Dorota [US/US]; (US) (For US Only)
Inventors: WILLIAMS, Charles, Kenneth; (US).
BOWER, Christopher, A.; (US).
MALTA, Dean, Michael; (US).
TEMPLE, Dorota; (US)
Agent: KUESTERS, Eckhard, H.; Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P 1940 Duke Street Alexandria, VA 22314 (US)
Priority Data:
61/166,388 03.04.2009 US
Title (EN) A THREE DIMENSIONAL INTERCONNECT STRUCTURE AND METHOD THEREOF
(FR) STRUCTURE D'INTERCONNEXION TRIDIMENSIONNELLE ET SON PROCÉDÉ
Abstract: front page image
(EN)A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
(FR)L'invention porte sur une interconnexion tridimensionnelle qui comprend un premier substrat collé à un second substrat, le premier substrat comprenant une couche de dispositif et une couche de semi-conducteur massif, un plot métallique agencé sur le second substrat, une couche électriquement isolante agencée entre les premier et second substrats. La structure comprend un trou d'interconnexion s'étendant à travers la couche de dispositif, la couche de semi-conducteur massif et la couche électriquement isolante jusqu'au plot métallique sur le second substrat. La structure porte un revêtement diélectrique sur une paroi latérale du trou d'interconnexion, et une région traitée par plasma du plot métallique agencée sur le second substrat. La structure comprend un métal de trou d'interconnexion s'étendant de façon monolithique à partir de la région traitée par plasma du plot métallique à travers le trou d'interconnexion et interconnectant électriquement la couche de dispositif du premier substrat au plot métallique du second substrat.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)