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1. (WO2010113539) CIRCUIT BOARD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/113539 International Application No.: PCT/JP2010/051488
Publication Date: 07.10.2010 International Filing Date: 03.02.2010
IPC:
H01L 23/12 (2006.01) ,H01L 23/14 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants: KATO Noboru[JP/JP]; JP (UsOnly)
MURATA MANUFACTURING CO., LTD.[JP/JP]; 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP (AllExceptUS)
Inventors: KATO Noboru; JP
Agent: MORISHITA Takekazu; Hommachi Eiwa Building 2-10, Minamihommachi 4-chome, Chuo-ku, Osaka-shi, Osaka 5410054, JP
Priority Data:
2009-08989702.04.2009JP
Title (EN) CIRCUIT BOARD
(FR) CARTE DE CIRCUITS IMPRIMÉS
(JA) 回路基板
Abstract:
(EN) A circuit board with a design which can minimize electronic components coming off of the circuit board. A multilayer structure (11) is formed by stacking a plurality of insulator layers (16) comprised from flexible material. External electrodes (12) are provided on the upper surface of the multilayer structure (11). An electronic component is mounted on the external electrodes (12). A plurality of inner conductors (20) overlap the external electrodes (12) when seen from a plan view from the z-axial direction, and, at the regions of overlap with the external electrodes (12), are not connected to each other by via hole conductors.
(FR) L'invention concerne une carte de circuits imprimés dont la conception permet de réduire le détachement des composants électroniques de la carte. Une structure à plusieurs couches (11) est formée en empilant une pluralité de couches isolantes (16) composées de matériau flexible. Des électrodes extérieures (12) sont disposées sur la surface supérieure de la structure à plusieurs couches (11). Un composant électronique est monté sur les électrodes extérieures (12). Une pluralité de conducteurs intérieurs (20) chevauchent les électrodes extérieures (12) quand ils sont observés depuis une vue en plan dans la direction axiale z, et, au niveau des régions de chevauchement avec les électrodes extérieures (12), ne sont pas raccordés les uns aux autres par des conducteurs de trou d'interconnexion.
(JA)  回路基板から電子部品が外れることを抑制できる回路基板を提供することである。 積層体(11)は、可撓性材料からなる複数の絶縁体層(16)が積層されることにより構成されている。外部電極(12)は、積層体(11)の上面に設けられる。該外部電極(12)には、電子部品が実装される。複数の内部導体(20)は、z軸方向から平面視したときに、外部電極(12)と重なっている複数の内部導体(20)であって、外部電極(12)と重なっている領域においてビアホール導体によって互いに接続されていない。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)