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1. (WO2010113377) DIGITAL FREQUENCY/PHASE LOCKED LOOP

Pub. No.:    WO/2010/113377    International Application No.:    PCT/JP2010/000711
Publication Date: Fri Oct 08 01:59:59 CEST 2010 International Filing Date: Sat Feb 06 00:59:59 CET 2010
IPC: H03L 7/107
H03L 7/10
Applicants: PANASONIC CORPORATION
パナソニック株式会社
MAEDA, Masakatsu
前田昌克
Inventors: MAEDA, Masakatsu
前田昌克
Title: DIGITAL FREQUENCY/PHASE LOCKED LOOP
Abstract:
A digital FLL/PLL able to converge an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor for each VCO gain. The digital FLL/PLL is provided with: a comparator for comparing a channel signal with a loopback signal having an oscillation frequency and generating a signal error; digital loop filters for generating a control voltage determining the oscillation frequency, based on the signal error; a VCO for controlling the oscillation frequency, based on the control voltage; a loopback route for outputting the oscillation frequency generated by the VCO as a loopback signal to the comparator; and a control unit for monitoring the signal error and, upon detecting that the signal error satisfies a predetermined condition after the channel signal has been changed, controlling the digital loop filters so that the oscillation frequency of the VCO becomes stable.