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1. (WO2010113229) SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/113229    International Application No.:    PCT/JP2009/006368
Publication Date: 07.10.2010 International Filing Date: 25.11.2009
IPC:
H01L 21/768 (2006.01), G09F 9/30 (2006.01), H01L 21/28 (2006.01), H01L 21/336 (2006.01), H01L 29/417 (2006.01), H01L 29/786 (2006.01)
Applicants: SHARP KABUSHIKI KAISHA [JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522 (JP) (For All Designated States Except US).
NAKAZAWA, Makoto; (For US Only).
MIYAMOTO, Mitsunobu; (For US Only)
Inventors: NAKAZAWA, Makoto; .
MIYAMOTO, Mitsunobu;
Agent: MAEDA, Hiroshi; (JP)
Priority Data:
2009-090747 03.04.2009 JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE PRODUCTION
(JA) 半導体装置及びその製造方法
Abstract: front page image
(EN)A semiconductor device having a planarization layer that is comprised by an inorganic film and formed with recesses at regions where a conductive film is disposed. A first contact hole running through at least an interlayer insulating film is formed on a first interconnect layer, while a second contact hole running through at least the interlayer insulating film is formed on the conductive film in a manner which has the second contact hole passing through the inward side of a recess.
(FR)L'invention concerne un dispositif semi-conducteur comportant une couche de planarisation qui est constituée d'une pellicule inorganique et formée avec des évidements dans des zones où une pellicule conductrice est disposée. Un premier trou de contact traversant au moins une pellicule isolante intercouche est formée sur une première couche d'interconnexion, tandis qu'un second trou de contact traversant au moins la pellicule isolante intercouche est formé sur la pellicule conductrice de telle manière que le second trou de contact traverse le côté intérieur d'un évidement.
(JA) 半導体装置は、無機膜によって構成されると共に導電性膜が配置されている領域で凹部が形成された平坦化層を有する。第1配線層上には、少なくとも層間絶縁膜を貫通する第1コンタクトホールが形成される一方、導電性膜上には、凹部の内側を通るように、少なくとも層間絶縁膜を貫通する第2コンタクトホールが形成されている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)