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1. WO2010091497 - TERMINATION CIRCUIT FOR ON-DIE TERMINATION

Publication Number WO/2010/091497
Publication Date 19.08.2010
International Application No. PCT/CA2010/000027
International Filing Date 11.01.2010
IPC
H03H 11/46 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
11Networks using active elements
46One-port networks
G11C 5/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/50 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50for integrated circuit devices
CPC
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H03K 19/0005
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0005Modifications of input or output impedance
H03K 19/00361
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
003Modifications for increasing the reliability ; for protection
00346Modifications for eliminating interference or parasitic voltages or currents
00361in field effect transistor circuits
H03K 3/012
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
01Details
012Modifications of generator to improve response time or to decrease power consumption
H04L 25/0278
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
02Details
0264Arrangements for coupling to transmission lines
0278Arrangements for impedance matching
Applicants
  • MOSAID TECHNOLOGIES INCORPORATED [CA]/[CA] (AllExceptUS)
  • GILLINGHAM, Peter, B. [CA]/[CA] (UsOnly)
Inventors
  • GILLINGHAM, Peter, B.
Agents
  • SMART & BIGGAR
Priority Data
61/151,88612.02.2009US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TERMINATION CIRCUIT FOR ON-DIE TERMINATION
(FR) CIRCUIT DE TERMINAISON POUR TERMINAISON SUR PUCE
Abstract
(EN)
In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.
(FR)
L'invention porte, dans un dispositif à semi-conducteurs ayant une borne connectée à une partie interne, sur un circuit de terminaison pour fournir une terminaison sur puce pour la borne du dispositif. Le circuit de terminaison comprend une pluralité de transistors, comprenant au moins un transistor NMOS et au moins un transistor MPOS, connectés entre la borne et une alimentation électrique ; et une circuiterie de commande pour attaquer une grille de chaque transistor NMOS par une tension de grille NMOS correspondante et pour attaquer une grille de chaque transistor PMOS par une tension de grille PMOS correspondante, la circuiterie de commande étant configurée pour commander les tensions de grille NMOS et PMOS de façon à placer les transistors dans une région de fonctionnement ohmique lorsqu'une terminaison sur puce est activée. L'alimentation électrique délivre une tension qui est inférieure à chaque tension de grille NMOS et supérieure à chaque tension de grille PMOS.
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