Processing

Please wait...

Settings

Settings

Goto Application

1. WO2010090746 - MANAGEMENT OF OVER-ERASURE IN NAND-BASED NOR-TYPE FLASH MEMORY

Publication Number WO/2010/090746
Publication Date 12.08.2010
International Application No. PCT/US2010/000318
International Filing Date 04.02.2010
IPC
G11C 29/52 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
G11C 16/34 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 16/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
CPC
G11C 11/5635
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5628Programming or writing circuits; Data input circuits
5635Erasing circuits
G11C 16/0441
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0408comprising cells containing floating gate transistors
0441comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
G11C 16/344
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3436Arrangements for verifying correct programming or erasure
344Arrangements for verifying correct erasure or for detecting overerased cells
Applicants
  • APLUS FLASH TECHNOLOGY, INC. [US]/[US] (AllExceptUS)
  • LEE, Peter, W. [US]/[US] (UsOnly)
Inventors
  • LEE, Peter, W.
Agents
  • ACKERMAN, Stephen, B.
Priority Data
61/207,02005.02.2009US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MANAGEMENT OF OVER-ERASURE IN NAND-BASED NOR-TYPE FLASH MEMORY
(FR) GESTION DU SUR-EFFACEMENT DANS UNE MÉMOIRE FLASH DE TYPE NON-OU FONDÉE SUR NON-ET
Abstract
(EN)
A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and erasing, erase verifying, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state. Other block sections are iteratively selected and erased, erased verified, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.
(FR)
L'invention porte sur un procédé et un appareillage pour exploiter un bloc de matrice de cellules de mémoire flash non-ou à transistor conservant une charge double, par effacement des cellules de mémoire flash non-ou à transistor conservant une charge double, pour définir leur niveau de tension de seuil dans le but d'empêcher une fuite du courant en conséquence de la corruption de données pendant une opération de lecture. L'effacement du bloc de matrice des cellules de mémoire flash non-ou commence par la sélection d'une section de bloc du bloc de matrice, et l'effacement, la vérification de l'effacement, la vérification du sur-effacement et la programmation itérative jusqu'à ce que les transistors de conservation de la charge aient leur tension de seuil comprise entre la limite inférieure et la limite supérieure du premier état de programmation. D'autres sections de bloc sont sélectionnées d'une manière itérative et effacées, soumises à une vérification d'effacement, à une vérification du sur-effacement et à une programmation, d'une manière répétée jusqu'à ce que les transistors de conservation de la charge aient leur tension de seuil située entre la limite inférieure et la limite supérieure du premier état de programmation, jusqu'à ce que la totalité du bloc ait été effacée et reprogrammée à un niveau de seuil positif.
Also published as
Latest bibliographic data on file with the International Bureau