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1. WO2010089814 - SEMICONDUCTOR SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE

Publication Number WO/2010/089814
Publication Date 12.08.2010
International Application No. PCT/JP2009/003722
International Filing Date 04.08.2009
IPC
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
CPC
H01L 2224/03828
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
03Manufacturing methods
038Post-treatment of the bonding area
03828Applying flux
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/05073
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05073Single internal layer
H01L 2224/05124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05117the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05124Aluminium [Al] as principal constituent
H01L 2224/05568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05568the whole external layer protruding from the surface
H01L 2224/05571
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05571the external layer being disposed in a recess of the surface
Applicants
  • パナソニック株式会社 PANASONIC CORPORATION [JP]/[JP] (AllExceptUS)
  • 仲野純章 NAKANO, Sumiaki (UsOnly)
Inventors
  • 仲野純章 NAKANO, Sumiaki
Agents
  • 前田弘 MAEDA, Hiroshi
Priority Data
2009-02342504.02.2009JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE
(FR) STRUCTURE DE SUBSTRAT SEMI-CONDUCTEUR ET DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体基板構造及び半導体装置
Abstract
(EN)
Provided is a semiconductor substrate structure wherein excessive spread of a flux to be printed can be eliminated. The semiconductor substrate structure is provided with an electrode pad (103) formed on a semiconductor substrate main body (100); a protecting film (123) formed on the semiconductor substrate main body (100) by being spaced apart from the electrode pad (103); and a bump (111) formed on the electrode pad (103).  The protecting film (123) has a barrier section (123a) which surrounds the electrode pad (103).  The barrier section (123a) has a height different from the heights of the sections other than the barrier section (123a) on the protection film (123).
(FR)
L'invention porte sur une structure de substrat semi-conducteur dans laquelle un étalement excessif d'un flux devant être imprimé peut être éliminé. La structure de substrat semi-conducteur comprend un plot d'électrodes (103) formé sur un corps principal de substrat semi-conducteur (100) ; un film protecteur (123), formé sur le corps principal de substrat semi-conducteur (100) en étant espacé à distance du plot d'électrodes (103) ; et une bosse (111 formée sur le plot d'électrodes (103). Le film protecteur (123) comprend une section barrière (123a) qui entoure le plot d'électrodes (103). La section barrière (123a) présente une hauteur différente des hauteurs des sections autres que la section barrière (123a) sur le film protecteur (123).
(JA)
 本発明は、印刷されるフラックスの過度な広がりを防止出来る半導体基板構造に関する。半導体基板構造は、半導体基板本体(100)の上に形成された電極パッド(103)と、半導体基板本体(100)の上に電極パッド(103)と間隔をおいて形成された保護膜(123)と、電極パッド(103)の上に形成されたバンプ(111)とを備えている。保護膜(123)は、電極パッド(103)を囲む障壁部(123a)を有している。障壁部(123a)は、保護膜(123)における障壁部(123a)を除く部分と高さが異なっている。
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