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1. WO2010087336 - METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAINED USING THE METHOD, METHOD OF CONNECTING SEMICONDUCTOR CHIPS, AND THREE-DIMENSIONAL STRUCTURE, ON THE SURFACE OF WHICH WIRING IS PROVIDED AND FABRICATION METHOD THEREOF

Publication Number WO/2010/087336
Publication Date 05.08.2010
International Application No. PCT/JP2010/050971
International Filing Date 26.01.2010
IPC
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/52 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
H01L 25/065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 25/07 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
07the devices being of a type provided for in group H01L29/78
H01L 25/18 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
CPC
G11B 5/486
GPHYSICS
11INFORMATION STORAGE
BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
5Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
48Disposition or mounting of heads ; or head supports; relative to record carriers
4806specially adapted for disk drive assemblies, e.g. assembly prior to operation, hard or flexible disk drives
486with provision for mounting or arranging electrical conducting means or circuits on or along the arm assembly
H01L 21/565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
H01L 22/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
22Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
10Measuring as part of the manufacturing process
12for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/05554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05554being square
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
Applicants
  • パナソニック電工株式会社 PANASONIC ELECTRIC WORKS CO., LTD. [JP]/[JP] (AllExceptUS)
  • 吉岡 愼悟 YOSHIOKA, Shingo [JP]/[JP] (UsOnly)
  • 藤原 弘明 FUJIWARA, Hiroaki [JP]/[JP] (UsOnly)
Inventors
  • 吉岡 愼悟 YOSHIOKA, Shingo
  • 藤原 弘明 FUJIWARA, Hiroaki
Agents
  • 小谷 悦司 KOTANI, Etsuji
Priority Data
2009-01505227.01.2009JP
2009-25313104.11.2009JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAINED USING THE METHOD, METHOD OF CONNECTING SEMICONDUCTOR CHIPS, AND THREE-DIMENSIONAL STRUCTURE, ON THE SURFACE OF WHICH WIRING IS PROVIDED AND FABRICATION METHOD THEREOF
(FR) PROCÉDÉ DE MONTAGE DE PUCES SEMI-CONDUCTRICES, DISPOSITIF À SEMI-CONDUCTEURS OBTENUS PAR CE PROCÉDÉ, PROCÉDÉ DE CONNEXION DE PUCES SEMI-CONDUCTRICES, ET STRUCTURE TRIDIMENSIONNELLE, À LA SURFACE DE LAQUELLE EST PRÉVU UN CÂBLAGE ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法
Abstract
(EN)
Provided is a method of mounting semiconductor chips, comprising a step of forming a resin coating (3) on the surface of a path connecting bonding pads (2a) on the surface of a semiconductor chip (2) and electrode pads (1a) formed on the surface of an insulating base material (1), a step of forming wiring gutters (4) having a depth equal to or larger than the thickness of the resin coating (3) using laser beam machining along the path for connecting the bonding pads (2a) and the electrode pads (1a), a step of laminating plating catalysts (5) on the surfaces of the wiring gutters (4), a step of removing the resin coating (3), and a step of forming electroless plating coatings (6) only on the sites in which the plating catalysts (5) remain. Also provided is a three-dimensional structure, on the surface of which a wiring is provided, characterized in that recessed grooves for the wiring are so formed on the surface of the three-dimensional structure as to extend across the adjacent surfaces of the solid structure which intersect one another, and at least portions of conductors for the wiring are embedded in the recessed grooves for the wiring.
(FR)
La présente invention concerne un procédé de montage de puces semi-conductrices, comprenant une étape de formation d'un revêtement de résine (3) à la surface d'un chemin reliant des plots de connexion (2a) à la surface de la puce semi-conductrice (2) et des plots d'électrode (1a) formés à la surface d'un matériau de base isolant (1) ; une étape de formation de goulottes de câblage (4) présentant une profondeur égale ou supérieure à l'épaisseur du revêtement de résine (3) au moyen d'un usinage par faisceau laser le long du chemin pour connecter les plots de connexion (2a) et les plots d'électrode (1a) ; une étape d'élimination du revêtement de résine (3) ; et une étape de formation de revêtements par placage anélectrolytique (6) uniquement sur les sites dans lesquels les catalyseurs pour placage (5) subsistent. L'invention concerne également une structure tridimensionnelle, à la surface de laquelle un câblage est prévu, caractérisée en ce que des rainures creuses pour le câblage sont formées à la surface de la structure tridimensionnelle de manière à s'étendre sur toutes les surfaces adjacentes de la structure solide qui s'entrecroisent, et au moins des parties de conducteurs pour le câblage sont incorporées dans les rainures creuses pour le câblage.
(JA)
 本発明の一局面は、半導体チップ2の表面のボンディングパッド2aと絶縁基材1の表面に形成された電極パッド1aとをつなぐ経路の表面に樹脂被膜3を形成する工程と、ボンディングパッド2aと電極パッド1aとを接続するための経路に沿って、樹脂被膜3の厚みと同じまたは厚み分以上の深さの配線溝4をレーザー加工により形成する工程と、配線溝4の表面にメッキ触媒5を被着させる工程と、樹脂被膜3を除去する工程と、メッキ触媒5が残留する部位のみに無電解メッキ膜6を形成する工程とを備える半導体チップの実装方法である。本発明の他の一局面は、表面に配線が設けられた立体構造物であって、立体構造物の表面に、立体構造物の相互に交差する隣接面間に亘って延びる配線用凹溝が形成され、前記配線用凹溝の中に配線用導体の少なくとも一部が埋め込まれていることを特徴とする立体構造物である。
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