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1. (WO2010085304) METHODS OF ENHANCING PERFORMANCE OF FIELD-EFFECT TRANSISTORS AND FIELD-EFFECT TRANSISTORS MADE THEREBY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/085304 International Application No.: PCT/US2009/068992
Publication Date: 29.07.2010 International Filing Date: 21.12.2009
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
VERSATILIS LLC [US/US]; 488 Ridgefield Road Shelburne, VT 05482, US (AllExceptUS)
JAIN, Ajaykumar, R. [US/US]; US (UsOnly)
Inventors:
JAIN, Ajaykumar, R.; US
Agent:
HELLER, Morgan, S.; Downs Rachlin Martin PLLC 199 main Street, P.O. Box 190 Burlington, VT 05402-0190, US
Priority Data:
12/393,49326.02.2009US
61/205,59222.01.2009US
Title (EN) METHODS OF ENHANCING PERFORMANCE OF FIELD-EFFECT TRANSISTORS AND FIELD-EFFECT TRANSISTORS MADE THEREBY
(FR) PROCÉDÉS D'AMÉLIORATION DE PERFORMANCE DE TRANSISTORS À EFFET DE CHAMP ET TRANSISTORS À EFFET DE CHAMP AINSI FABRIQUÉS
Abstract:
(EN) Methods of enhancing the performance of a field-effect transistor (FET) by providing a percolating network of metallic islands to the inversion layer of the FET so as to effectively reduce the channel length of the FET. The metal islands can be provided in a number of ways, including Volmer- Weber metallic film growth, breaking apart continuous metallic film, patterning metallic coating, dispersing metallic particles in a semiconducting material, applying a layer of composite particles having metallic cores and semiconducting shells and co-sputtering metallic and semiconducting materials, among others. FETs made using disclosed methods have a novel channel structures that include metallic islands spaced apart by semiconducting material.
(FR) L'invention porte sur des procédés d'amélioration de performance d'un transistor à effet de champ (TEC) par formation d'un réseau percolant d'îlots métalliques vers la couche d'inversion du TEC de façon à réduire efficacement la longueur de canal du TEC. Les îlots métalliques peuvent être formés de plusieurs façons, comprenant une croissance de film métallique Volmer-Weber, une rupture d'un film métallique continu, une formation de motifs d'un revêtement métallique, une dispersion de particules métalliques dans un matériau semi-conducteur, une application d'une couche de particules composites comprenant des âmes métalliques et des enveloppes semi-conductrices et une co-pulvérisation de matériaux métalliques et semi-conducteurs, entre autres. Des TEC fabriqués à l'aide des procédés décrits présentent une nouvelle structure de canal qui comprend des îlots métalliques espacés l'un de l'autre par un matériau semi-conducteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2389683JP2012516053KR1020110105874