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1. (WO2010084124) DIGITAL PHASE DETECTION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/084124 International Application No.: PCT/EP2010/050616
Publication Date: 29.07.2010 International Filing Date: 20.01.2010
IPC:
H03L 7/085 (2006.01) ,H03L 7/091 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
085
concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
085
concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
091
the phase or frequency detector using a sampling device
Applicants:
TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) [SE/SE]; S-164 83 Stockholm, SE (AllExceptUS)
SJÖLAND, Henrik [SE/SE]; SE (UsOnly)
Inventors:
SJÖLAND, Henrik; SE
Agent:
ÅKERMAN, Mårten; Ericsson AB Nya Vattentornet S-221 83 Lund, SE
Priority Data:
12/357,98622.01.2009US
Title (EN) DIGITAL PHASE DETECTION
(FR) DÉTECTION DE PHASE NUMÉRIQUE
Abstract:
(EN) A method of detecting a phase difference between a circuit output signal and a reference signal is useful in all digital phase locked loops. A plurality of feedback signals are generated from the circuit output signal by means of a process that includes phase interpolation, wherein the feedback signals are spaced apart from one another by a duration of time less than a period of the circuit output signal. At a moment in time, the number of feedback signals that are asserted (logic 1 or in alternative embodiments, logic 0) is counted. The count is indicative of the phase difference between the circuit output signal and the reference signal.
(FR) La présente invention porte sur un procédé de détection d'une différence de phase entre un signal de sortie de circuit et un signal de référence, lequel procédé est utile dans toutes les boucles à verrouillage de phase numérique. Une pluralité de signaux de rétroaction sont générés à partir du signal de sortie de circuit à l'aide d'un processus qui comprend une interpolation de phase, les signaux de rétroaction étant espacés l'un de l'autre par une durée inférieure à une période du signal de sortie de circuit. À un certain moment, le nombre de signaux de rétroaction qui sont affirmés (1 logique ou 0 logique dans d'autres modes de réalisation) est compté. Le total est indicatif de la différence de phase entre le signal de sortie de circuit et le signal de référence.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)