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1. (WO2010082342) SEMICONDUCTOR DEVICE, PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE, APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE, AND METHOD FOR EVALUATING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/082342 International Application No.: PCT/JP2009/050578
Publication Date: 22.07.2010 International Filing Date: 16.01.2009
Chapter 2 Demand Filed: 29.05.2009
IPC:
H01L 21/28 (2006.01) ,C23C 14/14 (2006.01) ,C23C 14/34 (2006.01) ,H01L 21/285 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
06
characterised by the coating material
14
Metallic material, boron or silicon
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
22
characterised by the process of coating
34
Sputtering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283
Deposition of conductive or insulating materials for electrodes
285
from a gas or vapour, e.g. condensation
Applicants:
竹内 康恭 TAKEUCHI, Yasutaka [JP/JP]; JP (UsOnly)
トヨタ自動車株式会社 TOYOTA JIDOSHA KABUSHIKI KAISHA [JP/JP]; 〒4718571 愛知県豊田市トヨタ町1番地 Aichi 1, Toyota-cho, Toyota-shi, Aichi 4718571, JP (AllExceptUS)
Inventors:
竹内 康恭 TAKEUCHI, Yasutaka; JP
Agent:
特許業務法人 快友国際特許事務所 KAI-U PATENT LAW FIRM; 〒4500002 愛知県名古屋市中村区名駅二丁目45番14号 日石名駅ビル7階 Aichi NISSEKI MEIEKI BUILDING 7F, 45-14, Meieki 2-chome Nakamura-ku, Nagoya-shi, Aichi 4500002, JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE, PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE, APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE, AND METHOD FOR EVALUATING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR, PROCESSUS DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR, APPAREIL DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR, ET PROCÉDÉ D'ÉVALUATION D'UN DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置、半導体装置の製造方法、半導体装置の製造装置、および半導体装置の評価方法
Abstract:
(EN) Provided is a process for fabricating a semiconductor device comprising a semiconductor substrate, and a rear electrode wherein a layer containing aluminum, a titanium layer, a nickel layer, and a nickel oxidation-prevention layer are laminated from the semiconductor substrate side. The titanium layer of the rear electrode is formed by performing sputtering while setting the partial pressure of oxygen at 5×10-6 Pa or less. The sputtering apparatus comprises a detector for detecting the partial pressure of oxygen, and a controller which makes it possible to perform sputtering in such an atmosphere where the partial pressure of oxygen is 5×10-6 Pa or less with reference to a detection value of the detector.
(FR) L'invention concerne un processus de fabrication d'un dispositif semi-conducteur comprenant un substrat semi-conducteur et une électrode arrière dans lequel une couche contenant de l'aluminium, une couche de titane, une couche de nickel et une couche de prévention d'oxydation de nickel sont stratifiées depuis le côté du substrat semi-conducteur. La couche de titane de l'électrode arrière est formée en réalisant une pulvérisation en réglant une pression partielle d'oxygène inférieure ou égale à 5×10-6 Pa. L'appareil de pulvérisation comprend un détecteur servant à détecter la pression partielle d'oxygène, et une commande qui permet de réaliser la pulvérisation dans une atmosphère dans laquelle la pression partielle d'oxygène est inférieure ou égale à 5×10-6 Pa en référence à une valeur de détection du détecteur.
(JA)  半導体基板と、半導体基板側からアルミニウム含有層、チタン層、ニッケル層、ニッケル酸化防止層が積層された裏面電極とを備えた半導体装置の製造方法を提供する。裏面電極のチタン層は、酸素分圧を5×10-6Pa以下としてスパッタリングを行うことによって形成される。スパッタリング装置は、酸素分圧を検知する検知装置と、検知装置の検知値を参照して酸素分圧を5×10-6Pa以下の雰囲気下でのスパッタリングを実施可能にする制御装置とを備えている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)