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1. (WO2010082239) COMPARATOR AND A/D CONVERTER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/082239 International Application No.: PCT/JP2009/003476
Publication Date: 22.07.2010 International Filing Date: 23.07.2009
IPC:
H03K 5/08 (2006.01) ,H03M 1/12 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
5
Manipulating pulses not covered by one of the other main groups in this subclass
01
Shaping pulses
08
by limiting, by thresholding, by slicing, i.e. combined limiting and thresholding
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
Applicants:
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
佐塚友彦 SATSUKA, Tomohiko; null (UsOnly)
中順一 NAKA, Junichi; null (UsOnly)
須志原公治 SUSHIHARA, Kouji; null (UsOnly)
Inventors:
佐塚友彦 SATSUKA, Tomohiko; null
中順一 NAKA, Junichi; null
須志原公治 SUSHIHARA, Kouji; null
Agent:
前田弘 MAEDA, Hiroshi; 大阪府大阪市中央区本町2丁目5番7号 大阪丸紅ビル Osaka-Marubeni Bldg.,5-7,Hommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410053, JP
Priority Data:
2009-00487113.01.2009JP
Title (EN) COMPARATOR AND A/D CONVERTER
(FR) COMPARATEUR ET CONVERTISSEUR ANALOGIQUE/NUMÉRIQUE
(JA) 比較器およびA/D変換器
Abstract:
(EN) A current lowering factor detection unit (2a) detects lowering of a power source voltage (VDD) of a dynamic comparator (1).  Upon detection of lowering of the power source voltage (VDD) by the current lowering factor detection unit (2a), a substrate bias control unit (3a) controls a substrate bias voltage (VBIAS3) of MOS transistors (m0a, m0b) constituting a comparison unit (10) and/or substrate bias voltages (VBIAS1, VBIAS2) of MOS transistors (m2a, m2b, m3a, m3b) constituting a positive feedback unit (20) in the direction that the threshold value voltage of the MOS transistor becomes smaller.
(FR) Un module de détection de facteur de réduction de courant (2a) détecte une réduction d'une tension d'alimentation (VDD) d'un comparateur dynamique (1). Dès la détection d'une réduction de la tension d'alimentation (VDD) par le module de détection de facteur de réduction de courant (2a), un module de commande de polarisation de substrat (3a) commande une tension de polarisation de substrat (VBIAS3) de transistors MOS (m0a, m0b) constituant un module de comparaison (10) et/ou des tensions de polarisation de substrat (VBIAS1, VBIAS2) de transistors MOS (m2a, m2b, m3a, m3b) constituant un module de rétroaction positive (20) dans un sens de réduction de la tension de seuil des transistors MOS.
(JA)  電流低下要因検出部(2a)は、ダイナミック型比較器(1)の電源電圧(VDD)の低下を検出する。基板バイアス制御部(3a)は、電流低下要因検出部(2a)によって電源電圧(VDD)の低下が検出されると、比較部(10)を構成するMOSトランジスタ(m0a,m0b)の基板バイアス電圧(VBIAS3),および/または,正帰還部(20)を構成するMOSトランジスタ(m2a,m2b,m3a,m3b)の基板バイアス電圧(VBIAS1,VBIAS2)を当該MOSトランジスタの閾値電圧が小さくなる方向に制御する。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)