Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2010082100) ENHANCING PROCESSING EFFICIENCY IN LARGE INSTRUCTION WIDTH PROCESSORS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/082100 International Application No.: PCT/IB2009/055923
Publication Date: 22.07.2010 International Filing Date: 23.12.2009
IPC:
G06F 9/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
ALTAIR SEMICONDUCTOR LTD [IL/IL]; 6 Haharash Street P.O. Box 7158 45240 Hod Hasharon, IL (AllExceptUS)
ALMOG, Edan [IL/IL]; IL (UsOnly)
SEMEL, Nohik [IL/IL]; IL (UsOnly)
BITRAN, Yigal [IL/IL]; IL (UsOnly)
COHEN, Nadav [IL/IL]; IL (UsOnly)
LIVNE, Yoel [IL/IL]; IL (UsOnly)
ZYSS, Eli [IL/IL]; IL (UsOnly)
Inventors:
ALMOG, Edan; IL
SEMEL, Nohik; IL
BITRAN, Yigal; IL
COHEN, Nadav; IL
LIVNE, Yoel; IL
ZYSS, Eli; IL
Agent:
D. KLIGLER I.P. SERVICES LTD; P.O. Box 33111 61330 Tel Aviv, IL
Priority Data:
12/354,03415.01.2009US
Title (EN) ENHANCING PROCESSING EFFICIENCY IN LARGE INSTRUCTION WIDTH PROCESSORS
(FR) AMÉLIORATION DE L'EFFICACITÉ DE TRAITEMENT DANS DES PROCESSEURS À GRANDE LARGEUR D'INSTRUCTION
Abstract:
(EN) A processor (20) includes one or more processing units (40), an execution pipeline (32) and control circuitry (28). The execution pipeline includes at least first and second pipeline stages (44, 48, 52) that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory (24) by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations. The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one of the pipeline stages without re-fetching the program instruction from memory.
(FR) Un processeur (20) comprend une ou plusieurs unités de traitement (40), un pipeline d'exécution (32) et un circuit de commande (28). Le pipeline d'exécution comprend au moins un premier et un second étage de pipeline (44, 48, 52) qui sont montés en cascade de sorte que les instructions de programme, spécifiant les opérations qui doivent être exécutées par les unités de traitement au cours des cycles successifs du pipeline, soient extraites d'une mémoire (24) par le premier étage de pipeline et transmises au second étage de pipeline, qui incite les unités de traitement à exécuter les opérations spécifiées. Le circuit de commande est couplé lorsqu'il est déterminé qu'une instruction de programme qui est présente dans le second étage de pipeline dans un premier cycle du pipeline doit être exécutée de nouveau pendant un cycle subséquent du pipeline afin d'inciter le pipeline d'exécution à réutiliser l'instruction de programme dans l'un des étages de pipeline sans extraire à nouveau l'instruction de programme de la mémoire.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2377014JP2012515388CN102282537IN4041/CHENP/2011