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1. (WO2010080342) PSEUDO DUAL-PORTED SRAM
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/080342 International Application No.: PCT/US2009/067663
Publication Date: 15.07.2010 International Filing Date: 11.12.2009
IPC:
G06F 15/167 (2006.01) ,G06F 12/06 (2006.01) ,G06F 13/00 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
16
Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
163
Interprocessor communication
167
using a common memory, e.g. mailbox
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
06
Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Applicants:
FULCRUM MICROSYSTEMS, INC. [US/US]; 26630 Agoura Road Calabasas, California 91302, US (AllExceptUS)
DAMA, Jonathan [US/US]; US (UsOnly)
LINES, Andrew [US/US]; US (UsOnly)
Inventors:
DAMA, Jonathan; US
LINES, Andrew; US
Agent:
VILLENEUVE, Joseph, M.; Weaver Austin Villeneuve & Sampson LLP P.O. Box 70250 Oakland, California 94612-0250, US
Priority Data:
12/340,02219.12.2008US
Title (EN) PSEUDO DUAL-PORTED SRAM
(FR) PSEUDO-MÉMOIRE VIVE STATIQUE À DOUBLE PORT
Abstract:
(EN) A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
(FR) L'invention porte sur une mémoire qui comprend une matière mémoire principale constituée de multiples blocs de mémoire à port unique connectés par des bus de lecture et d'écriture parallèles, et une mémoire de bande latérale équivalente à un bloc de mémoire à double port unique. Un état de logique de commande et d'étiquettes facilite un motif d'accès à la mémoire principale et à la mémoire de bande latérale, de telle sorte que la mémoire fonctionne comme une mémoire à double port complète, capable de lire et d'écrire deux adresses arbitraires quelconques sur le même cycle.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2368194JP2012513073