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1. (WO2010079816) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/079816 International Application No.: PCT/JP2010/050122
Publication Date: 15.07.2010 International Filing Date: 08.01.2010
IPC:
H01L 27/10 (2006.01) ,H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01) ,H01L 45/00 (2006.01) ,H01L 49/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
日本電気株式会社 NEC CORPORATION [JP/JP]; 東京都港区芝五丁目7番1号 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP (AllExceptUS)
多田 宗弘 TADA, Munehiro [JP/JP]; JP (UsOnly)
阪本 利司 SAKAMOTO, Toshitsugu [JP/JP]; JP (UsOnly)
波田 博光 HADA, Hiromitsu [JP/JP]; JP (UsOnly)
伴野 直樹 BANNO, Naoki [JP/JP]; JP (UsOnly)
Inventors:
多田 宗弘 TADA, Munehiro; JP
阪本 利司 SAKAMOTO, Toshitsugu; JP
波田 博光 HADA, Hiromitsu; JP
伴野 直樹 BANNO, Naoki; JP
Agent:
加藤 朝道 KATO, Asamichi; 神奈川県横浜市港北区新横浜3丁目20番12号加藤内外特許事務所内 c/o A. Kato & Associates, 20-12, Shin-Yokohama 3-chome, Kohoku-ku, Yokohama-shi, Kanagawa 2220033, JP
Priority Data:
2009-00403809.01.2009JP
Title (EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) Provided is a semiconductor device loaded with a variable resistance element that can increase reliability, increase density and prevent deterioration of insulating characteristics and yield. The semiconductor device has a variable resistance element inside a multilayer wiring layer on a semiconductor substrate. Said variable resistance element has a configuration wherein a variable resistance element film that changes resistance is interposed between an upper electrode and a lower electrode. Said multilayer wiring layer is provided at least with wiring that is electrically connected to said lower electrode and a plug that is electrically connected to said upper electrode. Said wiring also serves as said lower electrode (figure 1).
(FR) L'invention concerne un dispositif semi-conducteur monté sur un élément à résistance variable présentant des propriétés de fiabilité, de densité élevée et d'isolation, et capable d'empêcher une détérioration de rendement. Le dispositif semi-conducteur possède, à l'intérieur d'une couche de câblage à multiples épaisseurs sur un substrat semi-conducteur, un élément à résistance variable. L'élément à résistance variable susmentionné possède une structure dans laquelle, entre une électrode supérieure et une électrode inférieure, est intercalée une membrane d'élément à résistance variable dont la résistance varie. La couche de câblage à multiples épaisseurs susmentionnée met en œuvre au moins un câblage électriquement connecté à l'électrode inférieure susmentionnée, et une fiche électriquement connectée à l'électrode supérieure susmentionnée. Le câblage susmentionné sert également d'électrode inférieure susmentionnée ( Figure 1).
(JA)  本発明は、信頼化、高密度化、絶縁特性及び歩留まりの劣化防止が可能な抵抗変化素子を搭載した半導体装置を提供する。半導体基板上の多層配線層の内部に抵抗変化素子を有する半導体装置であって、前記抵抗変化素子は、上部電極と下部電極との間に、抵抗が変化する抵抗変化素子膜が介在した構成となっており、前記多層配線層は、少なくとも、前記下部電極と電気的に接続された配線と、前記上部電極と電気的に接続されたプラグと、備え、前記配線は、前記下部電極を兼ねる(図1)。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010079816US20110272664US20160284993