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1. (WO2010079740) PLASMA PROCESSING APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/079740 International Application No.: PCT/JP2010/000028
Publication Date: 15.07.2010 International Filing Date: 05.01.2010
IPC:
H01L 21/205 (2006.01) ,H01L 31/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
04
adapted as conversion devices
Applicants:
株式会社アルバック ULVAC, Inc. [JP/JP]; 神奈川県茅ヶ崎市萩園2500 2500, Hagisono, Chigasaki-shi, Kanagawa 2538543, JP (AllExceptUS)
若松貞次 WAKAMATSU, Sadatsugu [JP/JP]; JP (UsOnly)
亀崎厚治 KAMESAKI, Koji [JP/JP]; JP (UsOnly)
菊池正志 KIKUCHI, Masashi [JP/JP]; JP (UsOnly)
神保洋介 JIMBO, Yosuke [JP/JP]; JP (UsOnly)
江藤謙次 ETO, Kenji [JP/JP]; JP (UsOnly)
浅利伸 ASARI, Shin [JP/JP]; JP (UsOnly)
内田寛人 UCHIDA, Hiroto [JP/JP]; JP (UsOnly)
Inventors:
若松貞次 WAKAMATSU, Sadatsugu; JP
亀崎厚治 KAMESAKI, Koji; JP
菊池正志 KIKUCHI, Masashi; JP
神保洋介 JIMBO, Yosuke; JP
江藤謙次 ETO, Kenji; JP
浅利伸 ASARI, Shin; JP
内田寛人 UCHIDA, Hiroto; JP
Agent:
志賀正武 SHIGA, Masatake; 東京都千代田区丸の内一丁目9番2号 1-9-2, Marunouchi, Chiyoda-ku, Tokyo 1006620, JP
Priority Data:
2009-00402709.01.2009JP
Title (EN) PLASMA PROCESSING APPARATUS
(FR) APPAREIL DE TRAITEMENT AU PLASMA
(JA) プラズマ処理装置
Abstract:
(EN) Disclosed is a plasma processing apparatus which comprises: an electrode flange (4); a chamber (2) having an inner wall surface (34); an insulating flange (31) arranged between the electrode flange (4) and the chamber (2); a base member (3) which has a lateral surface (32) and is arranged within the chamber (2), and on which a substrate (10) is placed; an RF power supply (9) which is connected to the electrode flange (4) and applies a high-frequency voltage thereto; and insulating members (41, 42) which are arranged on at least either the lateral surface (32) of the base member (3), which faces the inner wall surface (34), or the inner wall surface (34), which faces the lateral surface (32) of the base member (3).
(FR) La présente invention a trait à un appareil de traitement au plasma qui comprend : une bride d’électrode (4) ; une chambre (2) dotée d’une surface de paroi intérieure (34) ; une bride isolante (31) disposée entre la bride d’électrode (4) et la chambre (2) ; un élément de base (3) qui est pourvu d’une surface latérale (32) et qui est disposé à l’intérieur de la chambre (2), et sur lequel un substrat (10) est placé ; un bloc d’alimentation RF (9) qui est connecté à la bride d’électrode (4) et qui applique une tension à haute fréquence à celle-ci ; et des éléments isolants (41, 42) qui sont disposés au moins sur la surface latérale (32) de l’élément de base (3), qui fait face à la surface de paroi intérieure (34), ou sur la surface de paroi intérieure (34), qui fait face à la surface latérale (32) de l’élément de base (3).
(JA)  このプラズマ処理装置は、電極フランジ(4)と、内壁面(34)を有するチャンバ(2)と、前記電極フランジ(4)と前記チャンバ(2)との間に配置された絶縁フランジ(31)と、側面(32)を有し、前記チャンバ(2)内に配置され、基板(10)が載置されるベース部材(3)と、前記電極フランジ(4)に接続され、高周波電圧を印加するRF電源(9)と、前記内壁面(34)に対向する前記ベース部材(3)の前記側面(32)及び前記ベース部材(3)の側面(32)に対向する前記内壁面(34)の少なくともいずれか一方に配置された絶縁部材(41,42)とを含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010079740CN102272893KR1020110089457