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1. (WO2010079448) SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH CONTROL LOGIC TO CONTROL ASSOCIATIVE COMPUTATIONS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/079448 International Application No.: PCT/IB2010/050045
Publication Date: 15.07.2010 International Filing Date: 07.01.2010
IPC:
G06F 12/00 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
Applicants:
ZIKBIT LTD. [IL/IL]; 9 Halamish St. North Industrial Zone P.O. Box 3109 30889 Caesarea, IL (AllExceptUS)
AKERIB, Avidan [IL/IL]; IL (UsOnly)
EHRMAN, Eli [IL/IL]; IL (UsOnly)
MEIR, Josh [IL/IL]; IL (UsOnly)
MEYASSED, Moshe [IL/IL]; IL (UsOnly)
ALPERN, Yair [IL/IL]; IL (UsOnly)
AGAM, Oren [IL/IL]; IL (UsOnly)
Inventors:
AKERIB, Avidan; IL
EHRMAN, Eli; IL
MEIR, Josh; IL
MEYASSED, Moshe; IL
ALPERN, Yair; IL
AGAM, Oren; IL
Agent:
SWIRSKY, Daniel J.; AlphaPatent Associates Ltd. 55 Reuven St. 99544 Beit Shemesh, IL
Priority Data:
61/143,16908.01.2009US
Title (EN) SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH CONTROL LOGIC TO CONTROL ASSOCIATIVE COMPUTATIONS
(FR) SYSTÈME, PROCÉDÉ ET APPAREIL POUR MÉMOIRE À LOGIQUE DE COMMANDE PERMETTANT DE CONTRÔLER DES CALCULS ASSOCIATIFS
Abstract:
(EN) An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and control logic to control the associative computation.
(FR) L'invention concerne un dispositif à circuits intégrés qui comprend un substrat à semi-conducteurs, un réseau de cellules de mémoire RAM, se trouvant sur le substrat dans une première série de colonnes et conçues pour le stockage de données, un étage de calcul qui comporte des cellules de mémoire associatives, se trouvant sur le substrat dans une deuxième série de colonnes, en communication avec les colonnes correspondantes de la première série de manière à recevoir les données de la part du réseau de cellules RAM et à effectuer un calcul associatif sur les données, et une logique de commande pour contrôler le calcul associatif.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)