Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2010079389) SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/079389 International Application No.: PCT/IB2009/055284
Publication Date: 15.07.2010 International Filing Date: 23.11.2009
IPC:
H01L 21/265 (2006.01) ,H01L 29/49 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.; No. 8, Li-Hsin Rd. 6 Science-Based Industrial Park Hsin-Chu, Taiwan 300-77, TW (AllExceptUS)
MUELLER, Markus [DE/BE]; GB (UsOnly)
SINGANAMALLA, Raghunath [IN/BE]; GB (UsOnly)
Inventors:
MUELLER, Markus; GB
SINGANAMALLA, Raghunath; GB
Priority Data:
09100027.312.01.2009EP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEURS
Abstract:
(EN) A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a centre of the channel region.
(FR) L'invention porte sur un dispositif à semi-conducteurs et sur un procédé de fabrication d'un empilement de grille pour un tel dispositif à semi-conducteurs. Le dispositif comprend un empilement de grille qui présente une couche d'isolation de grille installée sur une région de canal du dispositif, et une couche métallique qui est isolée de la région de canal par la couche d'isolation de grille. La couche métallique contient des impuretés modulant le travail d'extraction qui présentent un profil de concentration qui varie le long de la longueur de la couche métallique en allant de la région de source vers la région de drain. L'empilement de grille possède un premier travail d'extraction effectif au voisinage d'une région de source et/ou de la région de drain du dispositif et un second travail d'extraction effectif différent vers le centre de la région de canal.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20110291206CN102349133CN106169418