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1. (WO2010078340) SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/078340 International Application No.: PCT/US2009/069705
Publication Date: 08.07.2010 International Filing Date: 29.12.2009
IPC:
H01L 21/336 (2006.01) ,H01L 21/31 (2006.01) ,H01L 21/8239 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; Mail Stop 525 8000 South Federal Way Boise, ID 83707-0006, US (AllExceptUS)
GOSWAMI, Jaydeb [IN/US]; US (UsOnly)
Inventors:
GOSWAMI, Jaydeb; US
Agent:
JONES, Terry, S.; TRASKBRITT 230 South 500 East Suite 300 P.O. Box 2550 Salt Lake City, UT 84110-2550, US
Priority Data:
12/348,73705.01.2009US
Title (EN) SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES
(FR) DISPOSITIFS À SEMI-CONDUCTEURS COMPRENANT DES STRUCTURES À DEUX GRILLES ET PROCÉDÉS DE FORMATION DE TELS DISPOSITIFS À SEMI-CONDUCTEURS
Abstract:
(EN) Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.
(FR) L'invention porte sur des dispositifs à semi-conducteurs comprenant des structures à deux grilles et sur des procédés de formation de tels dispositifs à semi-conducteurs. Par exemple, des dispositifs à semi-conducteurs sont décrits qui comprennent un premier empilement de grilles pouvant comprendre une première structure de grille conductrice formée à partir d'un premier matériau, et un second empilement de grilles pouvant comprendre une structure diélectrique formée à partir d'un oxyde du premier matériau. Pour un autre exemple, des procédés sont également décrits qui comprennent la formation d'une couche de matériau diélectrique à constante diélectrique élevée sur un substrat semi-conducteur, la formation d'une première couche de matériau conducteur sur la couche de matériau diélectrique à constante diélectrique élevée, l'oxydation d'une partie de la première couche de matériau conducteur afin de convertir la partie de la première couche de matériau conducteur en une couche de matériau diélectrique, et la formation d'une seconde couche de matériau conducteur au-dessus à la fois de la couche de matériau conducteur et de la couche de matériau diélectrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN102272906KR1020110094143